Copyright: Interactive Image Technologies


Contents

Menu Reference    Lists menus and their commands.

Parts Bins    Describe components and instruments used to create a circuit.

Sources Parts Bin	Basic Parts Bin
Diodes Parts Bin	Transistors Parts Bin
Analog ICs Parts Bin	Mixed ICs Parts Bin
Digital ICs Parts Bin	Logic Gates Parts Bin
Digital Parts Bin	Indicators Parts Bin
Controls Parts Bin	Miscellaneous Parts Bin
Instruments

Simulation Hints   Information on circuit simulation, analysis capabilities of Electronics Workbench and troubleshooting tips.

Release Notes    Information specific to this release of Electronics Workbench.

Technical Support    How to get technical support.


Menu Reference

File Menu

Edit Menu

Circuit Menu

Analysis Menu

Window Menu

Help Menu


File Menu

New

Open

Save

Save As

Revert to Saved (Revert)

Import

Export

Print

Print Setup (Windows)

Exit (Windows)

Install (Windows)


New Command
File/New

   CTRL+N   [image] +N

Opens an untitled circuit window that can be used to create a circuit. If you made changes to the current circuit, you are prompted to save the current circuit before it is closed.

When you start Electronics Workbench, a new untitled circuit window is opened automatically.

Tip  The environment of a new circuit is determined by the default circuit Default.ewb (Windows) or Default Circuit (Macintosh). For information about the default circuit, see "Customizing the Application Window for All Circuits" in the User Interface chapter of your Electronics Workbench User's Guide.


Open Command
File/Open

   CTRL+O   [image] +O

Opens a previously created circuit file. Displays a standard open file dialog box. If necessary, change to the drive/directory or disk/folder that contains the file you want.

Note  You can open files with extensions .ca, .ca3, .cd3, .ca4 and .ewb (Windows). Macintosh users, see Appendix B of the Electronics Workbench User's Guide for instructions on opening files created on a PC.


Save Command
File/Save

   CTRL+S   [image] +S

Saves the current circuit file. Displays a standard file save dialog box. If you want, change to a different directory/drive or folder/disk.

For Windows users, the extension .ewb is added to the file name automatically. For example, a circuit named Mycir will be saved as Mycir.ewb.

Tip  To preserve the original circuit without changes, choose File/Save As.


Save As Command
File/Save As

Saves the current circuit with a new file name. The original circuit remains unchanged.

Tip  Use this command to experiment safely on a copy of a circuit, without changing the original.


Revert to Saved (Revert) Command
File/Revert to Saved (Revert)

Restores a circuit to the way it was when you last saved.


Import Command
File/Import

Imports a SPICE netlist (Windows extension .net or .cir) and converts it to a schematic.


Export Command
File/Export

For Windows users, saves the circuit file in the file format for any of the following extensions: .net, .scr, .cmp, .cir, .plc. For Macintosh users, the three characters of the extension are appended to the file's name.


Print Command
File/Print

   CTRL+P   [image] +P

Prints all or some aspects of a circuit and/or its instruments.

Select items to be printed, in the order in which you want them printed. Items will be printed more than one to a page, if space allows.

Note  Printing is always at 100%, regardless of the scale factor used to display the circuit.


Print Setup Command
File/Print Setup

Displays a standard Print Setup dialog box, from which you can switch to another installed printer and specify image orientation, paper size, paper source and other options. (For information on installing and configuring printers using Print Manager, see your Windows User's Guide.)

Tip  For circuits that are wider than they are tall, use landscape orientation.

Note  If a circuit is too big for one piece of paper, it will automatically be spread over the number of pages necessary to print it all.


Exit (Quit) Command
File/Exit (Quit)

ALT+F4   [image] +Q

Closes the current circuit and leaves Electronics Workbench. If you have unsaved changes, you are prompted to save the circuit.


Install Command
File/Install

Installs any add-on products for Electronics Workbench. Prompts for disk containing add-on product.


Edit Menu

Cut

Copy

Paste

Delete

Select All (Windows)

Copy as Bitmap (Windows)

Show Clipboard


Cut Command
Edit/Cut

   CTRL+X   [image] +X

Removes selected components, circuits or text. What you cut is placed on the Clipboard so you can paste it elsewhere.

Note   Cut is not available if selection includes instrument icons.


Copy Command
Edit/Copy

   CTRL+C   [image] +C

Copies selected components, circuits or text. The copy is placed on the Clipboard. You can then use the Paste command to paste the copy elsewhere.

Note  Copy is not available if selection includes instrument icons.

Caution  Whatever is on the Clipboard is replaced when a new selection is cut or copied. If you want to delete an object permanently, without losing the contents of the Clipboard, use the Delete command.


Paste Command
Edit/Paste

   CTRL+V   [image] +V

Places the contents of the Clipboard in the active window (contents remain on the Clipboard).

The contents of the Clipboard may be components or text. The information on the Clipboard can only be pasted into locations that can contain similar information. For example, you cannot paste a component into the description window.

Note  You cannot paste the contents of the Clipboard into Electronics Workbench if they were placed there using Edit/Copy as Bitmap.


Delete Command
Edit/Delete

DEL

Permanently removes selected components or text. Does not place the selection on the Clipboard and does not affect anything currently on the Clipboard.

Caution  Use the Delete command with care. Deleted information cannot be retrieved.

Note  Deleting a component or instrument removes it from the circuit window, not from the toolbar.


Select All Command (Windows)
Edit Select All (Windows)

Selects all items in the active window (circuit window, subcircuit window or description window). If an instrument is part of the selection, Edit/Copy  and Edit/Cut  are not available.

Tip  To select all but a few items, use the Select All command and then deselect the ones you do not want by CTRL-clicking with the mouse button (Windows) or by SHIFT-clicking (Macintosh).

For directions on selecting with a mouse, see the User Interface chapter of your Electronics Workbench User's Guide.


Copy as Bitmap Command
Edit/Copy as Bitmap

Copies bitmap image of items to the Clipboard. You can use these images in word processors or page layout programs.

To copy a bitmap image of items:

1.	Choose Edit/Copy as Bitmap. The cursor changes to a crosshair.

2.	Click and drag to form a rectangle enclosing everything you want to copy.

3.	Release the mouse button.

Note  You cannot use Edit/Paste to place these items within Electronics Workbench.


Show Clipboard Command
Edit/Show Clipboard

Displays contents of Clipboard.

The Clipboard is a temporary storage location for components or text you want to place elsewhere in a circuit. You can also use the Clipboard to transfer information from Electronics Workbench to another application.

The Clipboard can hold both graphics (components or circuits) and text. If the active window cannot hold the type of information that is on the Clipboard, or if the Clipboard is empty, the Edit/Paste command is not available. For example, if the Clipboard contains components, and a text insertion point is selected in the description window, the Paste command is dimmed.

To close the Clipboard, double-click its Control-menu (Windows) or close box (Macintosh).


Circuit Menu

Rotate

Flip Vertical

Flip Horizontal

Component Properties

Create Subcircuit

Zoom

Schematic Options


Rotate Command
Circuit/Rotate

   CTRL+R   [image] +R

Rotates the selected components 90 degrees clockwise. Text associated with the component, such as labels, values and model information, may be repositioned, but is not rotated. If necessary, wires attached to the component are rerouted automatically.

Exceptions  When you rotate the ammeter and voltmeter, only their terminals rotate.


Flip Vertical Command
Circuit/Flip Vertical

Flips selected components vertically on the circuit window.

Note  Any wires attached to the flipped component re-route themselves as necessary. Text associated with the component, such as labels, values and model information, may be repositioned, but is not flipped.


Flip Horizontal Command
Circuit/Flip Horizontal

Flips selected components horizontally on the circuit window.

Note  Any wires attached to the flipped component re-route themselves as necessary. Text associated with the component, such as labels, values and model information, may be repositioned, but is not flipped.


Component Properties Command
Circuit/Component Properties

Assigns properties to the selected component. Also available by double-clicking on a component. If invoked with the right mouse button pop-up menu, this assigns default properties for all components of the selected type subsequently used in this circuit. It does not affect any components already placed.

The tabs of the Circuit/Component Properties dialog box depend on the type of component selected.

Label Tab

Value Tab

Models Tab

Schematic Options Tab

Fault Tab

Node Tab

Display Tab

Analysis Setup Tab


Label Tab (Component Properties)

CTRL+L   [image] +L

Use this tab to set or change a component's label and reference ID (components such as connectors and grounds do not have reference IDs).

To control whether labels and reference IDs appear on the circuit in the circuit window use the Show/Hide tab of the Circuit/Schematic Options dialog box.

Tip  If you rotate or flip a component, its label may be repositioned. If, as a result, a wire runs through a label, you can shift the label to the right by adding several spaces before it in the Label field.

Tip  To attach general information to a circuit, enter text in the description window, available from the Window menu.

Note  Reference IDs are assigned by the system to uniquely identify a component. You may modify these if necessary, but they must remain unique. Reference IDs cannot be deleted.


Value Tab (Component Properties)

CTRL+U   [image] +U

The fields on this tab are component-specific. For details, see the Electronics Workbench Technical Reference.

To control whether values appear on the circuit in the circuit window, use the Show/Hide tab of the Circuit/Schematic Options dialog box.


Models Tab (Component Properties)

CTRL+M   [image] +M

Use this tab to choose the model used for the component and to edit, add or delete models and libraries.

Component models default to Ideal, which for most circuit simulations may be all you need. If you want to increase the accuracy of your test results, use a real-world model.

To control whether model names appear on the circuit in the circuit window, use the Show/Hide tab of the Circuit/Schematic Options dialog box.


Schematic Options Tab (Component Properties)

Used to set color for wire. Wire color is overridden by node color set in the Node tab.


Fault Tab (Component Properties)

CTRL+F   [image] +F

Use this tab to assign a fault to the terminals of a component.

Leakage - puts a resistance value, specified in the adjoining fields, in parallel with the selected terminals. This causes the current to leak past the terminals instead of going through them.

Short - puts a very low resistance between two terminals, so the component has no measurable effect on the circuit.

Open - puts a very high resistance on a terminal, as if the wire leading to that terminal was broken.


Node Tab (Component Properties)

Node ID - system-assigned name of node.

Use as Testpoint - specifies if node is to be considered a testpoint.

Set Node Color - overrides color set for individual wires.


Display Tab (Component Properties)

Use Schematic Options - when selected, uses display options on the Show/Hide tab of the Circuit/Schematic Options dialog box.

Show labels, Show models, Show reference ID - when "Use Schematic Options" unselected, display options are as specified.


Analysis Setup Tab (Component Properties)

Use global temperature - if selected, uses temperature set in Analysis/Analysis Options. If not selected, uses temperature as specified.

Set initial conditions - sets initial conditions for analysis of component.

Some components will display additional parameters on this tab, for use in conjunction with the analysis options described in the Electronics Workbench Technical Reference.


Create Subcircuit Command
Circuit/Create Subcircuit

   CTRL+B   [image] +B

Combines the selected items of a circuit into a subcircuit, in effect creating an integrated circuit.

A subcircuit can contain as many components as you want. Any wires leading to other components or connectors in the circuit will become terminals on the subcircuit icon.

To create a subcircuit:

1.	Select the items to be used for the subcircuit.

2.	Choose Circuit/Create Subcircuit, and complete the dialog that appears:

Copy from Circuit	places a copy of the selected components in the subcircuit. The original components remain as they are on the circuit window.

Move from Circuit 	removes the selected components from the circuit so they appear only in the subcircuit.

Replace in Circuit 	places the selected components in the subcircuit and replaces the selected components in the circuit with a rectangle labeled with the subcircuit's name.

The selected components appear in a new window, the subcircuit window. The name of the new subcircuit is added to the list of available subcircuits, which is displayed when the subcircuit icon is dragged from the Favorites toolbar. The subcircuit is available for the current circuit only. To make it available to all circuits created from now on, copy the subcircuit to, or create the subcircuit in, the default circuit file, as explained in the User Interface chapter of your Electronics Workbench User's Guide.


Zoom Command
Circuit/Zoom

Displays a sub-menu of choices for increasing or decreasing the display size of the circuit window.


Schematic Options Command
Circuit/Schematic Options

Controls the overall display of the circuit. Changes apply to the current circuit only. To make changes for all files, use the default circuit file. See the User Interface chapter of your Electronics Workbench User's Guide for details.

Grid Tab

Controls the display and use of the grid underlying the circuit window. Using the grid makes it easier to align items in the circuit. You can use the grid without displaying it. Displaying the grid causes the grid to appear in the background of the circuit window.

Show/Hide Tab

Controls the display of information on the circuit window. Selected items will be shown for the entire circuit, unless overridden for individual components using the Display tab of the Circuit/Component Properties dialog box.

Label Tab

Controls the font used for labels and reference IDs.

Value Tab

Controls the font used for values and models.


Analysis Menu

Activate

Pause

Resume

Stop

Analysis Options

DC Operating Point

AC Frequency

Transient

Fourier

Noise

Distortion

Parameter Sweep

Temperature Sweep

Pole-Zero

Transfer Function

Sensitivity

Worst Case

Monte Carlo

Graphs


Activate Command
Analysis/Activate

CTRL+G   [image] +G

Activates the circuit (turns on the power switch). Activating a circuit starts a sequence of mathematical operations to compute values for the testpoints in the circuit.

The power switch remains turned on (at "1") until you stop or pause the simulation.

Tip  You can also activate a digital circuit from the word generator.


Pause and Resume Commands
Analysis/Pause and Analysis Resume

F9   [image] +J

Temporarily interrupts or resumes a simulation (controls the Pause/Resume button). Pausing is useful if you want to take a longer look at a waveform or make changes to an instrument setting. (The simulation of simple circuits may be too quick to pause.)

Tip  You can pause the oscilloscope automatically by turning on Pause after each screen in the Instruments tab of the Analysis/ Analysis Options dialog box.


Stop Command
Analysis/Stop

CTRL+T   [image] +T

Manually stops simulation. Has same effect as clicking the power switch.

Note  Turning off the power erases data and instrument traces and resets all values to initial conditions.


Global Analysis Options
Global Options

Code	Option Name	Description	Default	Unit	Recommendation
ABSTOL	Absolute current tolerance	Resets the absolute current error tolerance. Default suitable for most bipolar transistor VLSI circuits.	1.0e-12	A	Generally, set to 6 to 8 orders of magnitude smaller than the largest current signal in the circuit. For example, for MOS circuits, change this value to    1.0e-10A.
GMIN	Minimum conductance	Resets the minimum conductance used in any circuit branch. Cannot be zero. Increasing this may positively improve the convergence of the solution: however, it will also negatively affect simulation accuracy.	1.0e-12	mho	Do not change default.
PIVREL	Pivot relative ratio	Resets the relative value between the largest column entry in the matrix and an acceptable pivot value. Value must be between 0 and 1.	0.001	-	Do not change default.
PIVTOL	Pivot absolute tolerance	Resets the absolute minimum value for a matrix entry to be accepted as a pivot.	1.0e-13	-	Do not change default.
RELTOL	Relative error tolerance	Resets the relative error tolerance of the simulation, which is the universal accuracy control. The value can significantly affect the convergence of the solution and the simulation speed. Value must be between 0 and 1.	0.001	-	Use typical values between     1.0e-06 and 0.01.
TEMP	Simulation temperature	Resets the temperature at which the entire circuit will be simulated. Setting in Analysis/ Temperature Sweep will override.	27	°C	-
VNTOL	Absolute voltage tolerance	Resets the absolute voltage error tolerance of the program.	1.0e-06	V	Generally, set to 6 to 8 orders of magnitude smaller than the largest voltage signal in the circuit.
CHGTOL	Charge tolerance	Resets the charge tolerance in coulombs.	1.0e-14	C	Do not change default.
RAMPTIME	Ramp time	Ramps independent sources, capacitor and inductor initial conditions from zero to their final values during the time period specified.	0	s	-
CONVSTEP	Relative steps size limit convergence	Controls automatic convergence assistance by establishing a relative step size limit in solving for the DC operating point.	0.25	-	-
CONVABS-STEP	Absolute step size limit convergence	Controls automatic convergence assistance by establishing an absolute step size limit in solving for the DC operating point.	0.1	-	-
CONVLIMIT	Convergence limit	Enables/disables a convergence algorithm used in some built-in component models.	ON	-	-
RSHUNT	Analog node shunt resistance	Inserts resistors to ground at all analog nodes in the circuit. Reducing value reduces simulation accuracy.	Disabled (1.0e12 when enabled)	Ω	Should be set to some very high resistance, say 1e+12Ω. If you get a "No DC path  to ground" or a "Matrix is nearly singular" error message, try decreasing RSHUNT to 1e+9Ω or 1e+6Ω.
	Temporary file size for simulation	Allows you to adjust the file size for storage of simulation results. When the file reaches its maximum size, a dialog appears from which you can choose to stop simulation, use remaining disk space and continue, or discard existing data and continue.	10	Mb	If your circuit has many nodes and you want to scroll the oscilloscope back in time to the start of the simulation, you may need to increase the temporary file size.


DC Analysis Options

Code	Option Name	Description	Default	Unit	Recommendation
ITL1	Operating point analysis iteration	Resets the upper bound limit to the number of Newton-Raphson iterations during a DC operating point analysis.	100	-	If you receive an error message "No convergence in DC analysis", increase the ITL1 value to 500 or 1000 and rerun the analysis.
GMINSTEPS	Steps in GMIN stepping algorithm	Sets the number of steps in the Gmin stepping algorithm. Helps find a solution during a   DC operating point analysis.  If a zero value is  specified, the Gmin stepping  algorithm is disabled.	10	-	-
SCRSTEPS	Steps in source stepping algorithm	Sets the number of steps in the source stepping algorithm. Helps find a solution during a DC operating point analysis.	10	-	-


Transient Analysis Options

Code	Option Name	Description	Default	Unit	Recommendation
ITL4	Transient time point iterations	Resets the upper bound limit to the number of Newton-Raphson iterations at each transient time point. Increasing the value may slow down transient simulation time. Decreasing the value increases the chance of nonconvergence.	10	-	If you receive an error message "Time step too small" or "No convergence in the transient analysis",  increase the ITL4 value to 15  or 20 and rerun the analysis.
MAXORD	Maximum order for integration method	Sets the maximum order for integration when GEAR chosen as transient analysis integration method. Must be between 2 and 6. Using a higher order theoretically leads to more accurate results, but slows down simulation.	2	-	Use the default value for most circuit simulation.
TRTOL	Transient error tolerance factor	Resets transient error tolerance. Only used in the local truncation error criterion.	7	-	Use default value
METHOD	Transient analysis	Selects integration method for transient analysis. Default provides faster simulations with same numerical accuracy, but can produce unintended oscillations.	TRAP-EZOIDAL	-	Use GEAR (gear integration method) if unwanted numerical oscillations occur during simulation or if circuit contains ideal switches. Use default if circuit operates in oscillation mode, for example, oscillator circuits. Be aware that Gear integration may overdamp the result.
ACCT	Print statistical	Turns on/off display of statistical data on simulation- related information. Data may be useful for debugging simulation- related problems. Data appear in the Analysis Graphs window.	Off	-	-


Device Analysis Options

Code	Option Name	Description	Default	Unit	Recommendation
DEFAD	MOS drain diffusion area	Resets the value for MOS drain diffusion area.	0	m2	Use default value unless you know how to specify a value from a MOS device datasheet.
DEFAS	MOS source diffusion area	Resets the value for MOS source diffusion area.	0	m2	Use default value unless you know how to specify a value from a MOS device datasheet.
DEFL	MOS channel length	Resets the value for MOS channel length.	0.0001	μm	Use default value unless you know how to specify a value from a MOS device datasheet.
DEFW	MOS channel width	Resets the value for MOS channel width.	0.0001	μm	Use default value unless you know how to specify a value from a MOS device datasheet.
TNOM	Model parameters normal temperature	Resets the normal temperature Resets the normal temperature at which model parameters are measured or calculated.	27	°C	Do not change unless you want your circuit to match data book specifications that were extracted at a temperature other than 27 °C.
BYPASS	Nonlinear model evaluation device bypass	Turns off/on the device bypass scheme for nonlinear model evaluation. Selecting off may increase simulation time.	On	-	Do not change default.
TRYTO-COMPACT	Compact transmission lines data	Applicable only to lossy transmission line component.  When option turned on, Electronics Workbench tries to  reduce data storage and memory  usage needed for transient simulation  of circuits containing lossy transmission lines.	Off	-	-


Instruments Analysis Options

Option Name	Description	Default	Unit	Recommendation
Oscilloscope - Points per cycle	Resets point per cycle on the oscilloscope Maximum time step (TMAX) is the reciprocal of points per cycle times frequency.	100	-	Reduce value to speed up simulation, however accuracy may be reduced.
Oscilloscope - Pause after each screen	Pauses simulation when the waveforms reach the right edge of the oscilloscope display area.	Disabled	-	Also use Analysis/Pause to interrupt drawing of waveforms at any point on the oscilloscope display.
Oscilloscope - Transient analysis maximum timestep	Places upper bond on timestep.	Disabled	s	Set value to Tstep or 2*Tstep. Decrease for more accuracy.
Oscilloscope - Set to zero	Tells transient analysis to set initial conditions to zero.	Off	-
Oscilloscope - Use initial conditions	Tells transient analysis to use user-defined initial conditions.	Off	-
Oscilloscope - Calculate DC operating pt.	Tells transient analysis to use DC operating point.	On	-
Bode plotter - Points per cycle	Controls numbers of points analyzed per cycle for Bode plot.	100	-	Increasing number also increases time needed to simulate a circuit. Use default whenever possible. If solution cannot be reached during simulation, lower to 50 or 100 and activate again.
Logic analyzer - Pre-trigger samples	Number of data points stored before logic analyzer is triggered.	100	-	Increase value to display more data before triggering.
Logic analyzer - Post-trigger samples	Number of data points stored after logic analyzer is triggered.	1000	-	Increase value to display more data.
Logic analyzer - Threshold voltage	Threshold above which an input signal to the logic analyzer is displayed as high or 1. Signals below threshold are display as low or 0. Default appropriate for most TTL circuits.	3.5	V	May need to change value for other circuit types, for example, CMOS, ECL.


Analysis Options Command
Analysis/Analysis Options

CTRL+Y   [image] +Y

Electronics Workbench lets you control many aspects of the simulation, such as resetting error tolerances, selecting simulation techniques and viewing the results. Simulation efficiency is also dependent on the options you choose (Global Options,  DC Analysis Options,  Transient Analysis Options, Device Analysis Options, and Instruments Analysis Options). Most options have default values.

To view or change any of the options, choose Analysis/Analysis Options.


Window Menu

Arrange

Bring Instruments to Front (Macintosh)

Bring Subcircuits to Front (Macintosh)

Circuit

Description


Arrange Command
Window/Arrange

CTRL+W   [image] +K

Neatly organizes the open windows.


Bring Instruments to Front Command (Macintosh)
Window/Bring Instruments to Front (Macintosh)

+I

Brings all open instruments to the front. If instruments obscure each other, click the title bar of the one you want to see, or drag to rearrange them.


Bring Subcircuit to Front Command (Macintosh)
Window/Bring Subcircuit to Front (Macintosh)

+W

Brings all open subcircuit windows to the front.


Circuit Command
Window/Circuit

Brings the circuit window to the front.


Description Command
Window/Description

CTRL+D

Opens the description window. (If the description window is already open, brings it to the front.) You can type comments or directions in the description window, or paste text from another application or circuit description.


Help Menu

F1   [image] +?

Contains commands that display this on-line help.

Tip  If you want to be able to refer to Help information as you work on a circuit, use the Keep Help on Top function in the Help window's Options menu.


DC Operating Point Analysis
Analysis/DC Operating Point

DC operating point analysis determines the DC operating point of a circuit. For DC analysis, AC sources are zeroed out and steady state is assumed, that is, capacitors are open circuits and inductors are short circuits. The results of DC analysis are usually intermediate values for further analysis. For example, the DC operating point obtained from DC analysis determines approximate linearized, small-signal models for any nonlinear components such as diodes and transistors for the AC frequency analysis.

Assumptions  Digital components are treated as large resistances to ground.

To set up the analysis, choose Analysis/DC Operating Point. There are no options to set.

Viewing the Results

Results are displayed in a chart that appears when the analysis has finished. The chart lists node DC voltages and branch currents.


AC Frequency Analysis
Analysis/AC Frequency

In AC frequency analysis, the DC operating point is first calculated to obtain linear, small-signal models for all nonlinear components. Then a complex matrix (containing both real and imaginary components) is created. To construct a matrix, DC sources are given zero values. AC sources, capacitors, and inductors are represented by their AC models. Nonlinear components are represented by linear AC small-signal models, derived from the DC operating point solution. All input sources are considered to be sinusoidal. The frequency of the sources is ignored. If the function generator is set to a square or triangular waveform, it will automatically switch internally to a sinusoidal waveform for analysis. AC frequency analysis then calculates the AC circuit response as a function of frequency.

Assumptions  Analog circuit, small-signal. Digital components are treated as large resistances to ground.

To perform the analysis:

1.	Review your circuit and decide on the nodes for analysis. You can specify magnitude and phase of a source for AC frequency analysis by double-clicking the source and choosing the Analysis Setup tab.

2.	Choose Analysis/AC Frequency.

3.	Enter or change items in the dialog box.

4.	Click Simulate (press ESC to stop the analysis).

Viewing the Results

The result of the AC frequency analysis is displayed on two graphs: gain versus frequency and phase versus frequency. These graphs appear when the analysis has finished.

If you have the Bode plotter connected to your circuit and turn on the power switch, a similar analysis is performed.


AC Frequency Analysis Dialog Box
AC Frequency Analysis Dialog Box Items

Item	Default	Unit	Notes
Start frequency	1	Hz	Start frequency for the sweep.
End frequency	10	GHz	End frequency for the sweep.
Sweep type	Decade	-	Decade/Linear/ Octave.
Number of points/ Points per	100	-	For linear, number of points between start and end.
Vertical scale	Log		Linear/Logarithmic/ Decimal. Controls y-axis scaling on output graph.
Nodes for analysis	-	-	Points in circuit for which you want to see results. Refers to node ID, not the node's label.


Transient Analysis
Analysis/Transient

In transient analysis, also called time-domain transient analysis, Electronics Workbench computes the circuit's response as a function of time. Each input cycle is divided into intervals, and a DC analysis is performed for each time point in the cycle. The solution for the voltage waveform at a node is determined by the value of that voltage at each time point over one complete cycle.

DC sources have constant values; AC sources have time-dependent values. Capacitors and inductors are represented by energy storage models (see Capacitor and Inductor in the Basic Parts Bin chapter). Numerical integration is used to calculate the quantity of energy transfer over an interval of time.

If Calculate DC operating point is selected in the dialog box, then Electronics Workbench first calculates the DC operating point of the circuit. Then, the DC analysis result is used as the initial conditions of the transient analysis. If Set to zero is selected, the transient analysis starts from zero initial conditions. If User-defined initial conditions is selected, the analysis starts from initial conditions as set in the component properties dialog boxes.

Assumptions  None.

To perform the analysis:

1.	Review your circuit and decide on nodes for analysis.

2.	Choose Analysis/Transient.

3.	Enter or change items in the dialog box.

4.	Click Simulate (press ESC to stop the analysis).

Viewing the Results

The result of the transient analysis is a graph of voltage versus time. This graph appears when the analysis has finished.

If you have the oscilloscope connected to your circuit and turn on the power switch, a similar analysis is performed.


Transient Analysis Dialog Box
Transient Analysis Dialog Box Items

Item	Default	Unit	Notes
Set to zero	Disable	-	Choose this if you want to start from zero initial conditions.
User-defined	Disable	-	Choose this if you want to start from the user-defined initial conditions.
Calculate DC operating point	Enable	-	Choose this if you want to start the analysis at DC operating point.
Start time	0	s	Start of transient analysis. Must be greater than or equal to 0 and less than Stop time.
Stop time	0.001	s	End of transient analysis. Must be greater than Start time.
Generate time steps automatically	Enabled		Electronics Workbench will attempt to choose a reasonable time step and maximum time step for circuit simulation.
Minimum number of points	100 Enabled	-	Number of points between start and stop times for simulation output and graphing.
Printing time step	1e-05 Disabled	s	Time interval for simulation output and graphing.
Maximum time step	1e-05 Disabled	s	Maximum time step that the simulation can take.
Nodes for analysis	-	-	Points in circuit for which you want to see results.


Fourier Analysis
Analyis/Fourier

Fourier analysis evaluates the DC, fundamental and harmonic components of a time-domain signal. The analysis performs a Discrete Fourier Transform on the results of a time-domain analysis. This decomposes a time-domain voltage waveform into its frequency-domain components. Electronics Workbench automatically performs a time-domain analysis to generate the Fourier analysis results.

You must select an output node in the dialog box. The output variable is the node from which the analysis extracts the voltage waveform.

The analysis also requires a fundamental frequency, which should be set to the frequency of an AC source in your circuit. If you have several AC sources in your circuit, you can set the fundamental frequency to the lowest common factor of the frequencies. For example, if you have a 10.5 kHz source and a 7 kHz source, set the fundamental frequency to 0.5 kHz.

Assumptions  None.

To perform the analysis:

1.	Review your circuit and decide on a node for analysis.

2.	Choose Analysis/Fourier.

3.	Enter or change items in the dialog box.

4.	Click Simulate (press ESC to stop the analysis).

Viewing the Results

Fourier analysis produces a graph of Fourier voltage component magnitudes and, optionally, phase components versus frequency. The magnitude plot is a bargraph by default but may be selected to be a line graph.


Fourier Analysis Dialog Box
Fourier Analysis Dialog Box Items

Item	Default	Unit	Notes
Output variable	A node in your circuit.	−	Point in the circuit for which you want to see results.
Fundamental	1	Hz	Frequency for which Fourier analysis frequency evaluates harmonics. Use an AC source's  frequency or lowest common factor.
Number of harmonics	9	−	Number of harmonics of the fundamental frequency that are calculated.
Vertical scale	Linear	−	Linear/Logarithmic/ Decibel.
Display phase	Disabled	−	When enabled, causes analysis to plot graphs of phase versus frequency.
Output as line	Disabled	−	When enabled, causes analysis to plot the magnitude as a line graph instead of a bargraph.


Noise Analysis
Analysis/Noise

Noise analysis is used to detect the magnitude of noise power in the output of electronic circuits. The analysis calculates the noise contributions from resistors and semiconductors. Each noise source is assumed to be statistically uncorrelated to the other noise sources in the circuit and their values are calculated independently. The total noise is the RMS sum of the individual noise contributions. The contribution of each noise generator to the specified output node is calculated.

For example, if you choose V1 as the "Input noise reference source" from the Noise Analysis dialog box, and N1 as the "Output node", then all the noise generators in the circuit have their noise contributions summed at N1 to provide the output noise. This value is then divided by the gain from V1 to N1 to get the equivalent input noise which, if injected from V1 into a noiseless circuit, would cause the previously calculated amount of output noise at N1.

Assumptions  Analog small-signal circuit. Non-conforming parts are ignored. Noise models for SPICE components are used.

To perform the analysis:

1.	Review your circuit and decide on an input noise reference source, output node and reference node.

2.	Choose Analysis/Noise.

3.	Enter or change other items in the dialog box.

4.	Click Simulate (press ESC to stop the analysis).

Viewing the Results

Noise analysis produces an output noise spectrum and an input noise spectrum and, optionally, a component contribution spectrum. Results are displayed as a graph of voltage squared, V2, versus frequency. The graph appears when the analysis is finished.


Noise Analysis Dialog Box
Noise Analysis Dialog Box Items

Item	Default	Unit	Notes
Input noise reference source	A source in your circuit.	−	Choose an AC voltage source as input.
Output node	A node in your circuit.	−	This is the node at which all noise contributions will be summed.
Reference node	0 (ground)	-	Reference voltage.
Start frequency	1	Hz	Start frequency for the sweep.
End frequency	10	GHz	End frequency for the sweep.
Sweep type	Decade	−	Decade/Linear/ Octave
Number of points/ Points per	100	−	For linear, number of frequency points between start and end frequencies.
Vertical scale	Log	−	Logarithmic/Linear/ Decibel.
Set points per summary	Disabled	−	When enabled, generates a trace of the selected component's noise  contribution. Number of frequency steps is divided by the points per summary, which reduces the resolution of the output graph.
Points per summary component	A component in your circuit.	−	When points per summary is enabled, selects the noise generator contribution to summarize.


Distortion Analysis
Analysis/Distortion

Distortion analysis measures harmonic distortion and intermodulation distortion products. If the circuit has one AC frequency, the analysis determines the complex values of the second and third harmonics at every point in the circuit. If the circuit has two AC frequencies, the analysis finds the complex values of the circuit variables at three different frequencies: at the sum of the frequencies, at the difference of the frequencies, and at the difference of the smaller frequency from the second harmonic of the larger one.

The analysis does a small-signal distortion analysis of the circuit.   A multi-dimensional Volterra analysis is done using multi-dimensional Taylor series to represent the nonlinearities at the operating point. The series expansion uses terms of up to third order.

Distortion analysis is useful for investigating small amounts of distortion which are normally unresolvable in the transient analysis.

Assumptions  Analog circuit, small-signal. Non-conforming parts are ignored. Distortion models for SPICE components are used.

To perform the analysis:

1.	Review your circuit and decide on one or two sources and one or more nodes for analysis. You can also change the magnitude and phase of sources for distortion analysis by double-clicking them in the circuit window and choosing the Analysis setup tab.

2.	Choose Analysis/Distortion.

3.	Enter or change items in the dialog box.

4.	Click Simulate (press ESC to stop the analysis).

If F2/F1 ratio is disabled, the analysis calculates harmonic distortion of one frequency which is swept according to the dialog box entries. If F2/F1 ratio is enabled, a spectral analysis is performed. Each independent source in the circuit may potentially have two (superimposed) sinusoidal inputs for distortion, at frequencies F1 and F2.

Viewing the Results

If the F2/F1 ratio is disabled, the analysis graphs the second and third harmonics. These graphs appear in the Distortion tab of Analysis/Display Graphs. If the F2/F1 ratio is enabled, the analysis graphs the selected voltage or branch current at the intermodulation frequencies, F1 + F2, F1 − F2, 2*F1 − F2, versus the swept frequency, F1. These graphs appear in the IM Distortion tab of Analysis/Display Graphs.


Distortion Analysis Dialog Box
Distortion Analysis Dialog Box Items

Item	Default	Unit	Notes
Start frequency	1	Hz	Starting frequency for the sweep.
End frequency	10	GHz	Ending frequency for the sweep.
Sweep type	Decade	−	Decade/Linear/ Octave
Number of points/ Points per	100	−	For linear, number of frequency points between start and end.
Vertical scale	Log	−	Logarithmic/Linear/ Decibel.
F2/F1 ratio	Disabled	0.9	If there are signals of two frequencies, F1 and  F2, then, when enabled, F2 is set to this ratio multiplied by the start frequency while F1 sweeps. Must be greater than 0.0 and less than 1.0.
Nodes for analysis	−	−	Points in circuit for which you want to see results.


Parameter Sweep Analysis
Analysis/Parameter Sweep

Using parameter sweep analysis, you can quickly verify the operation of your circuit by simulating it across a range of values for a component parameter. The effect is the same as simulating the circuit several times, once for each different value. You control the parameter values by choosing start, end and increment values in the Parameter Sweep dialog box.

Assumptions  See selected analysis (DC operating point, transient, or AC frequency).

To perform the analysis:

1.	Review your circuit and decide on a component and parameter to sweep, and a node for analysis.

2.	Choose Analysis/Parameter Sweep.

3.	Choose between DC Operating Point, Transient or AC Frequency analyses.

4.	Enter or change items in the dialog box.

5.	Click Simulate (press ESC to stop the analysis).

Note  If you choose transient analysis or AC frequency analysis you can view and modify the parameters of those analyses by clicking on the Set transient options button or the Set AC options button, respectively. This will open another dialog box in which you can change the parameters for the analysis.

Viewing the Results

Parameter sweep analysis plots the appropriate curves sequentially. If the sweep type is linear, the number of curves is equal to the difference between the start and end values divided by the increment step size. If the sweep type is decade, the number of curves is equal to the number of times the start value can be multiplied by ten before reaching the end value. If the sweep type is octave, the number of curves is equal to the number of times the start value can be doubled before reaching the end value.


Parameter Sweep Analysis Dialog Box
Parameter Sweep Analysis Dialog Box Items

Item	Default	Unit	Notes
Component	A component in your circuit	−	Component you want to sweep.
Parameter	1st parameter of component	−	Component's parameter you want to sweep.
Start value	Parameter value of selected component	−	Starting value for sweep.
End value	Parameter value of selected component	−	Ending value for sweep.
Sweep type	Decade	−	Decade/Linear/ Octave.
Increment step size	1	Depends on parameter	For linear sweep type only. Step size for sweep.
Output node	A node in your circuit	−	Point in circuit for which you  want to see results.
Sweep for:	Transient Analysis	−	DC Operating Point/ Transient Analysis/ AC Frequency Analysis (See Note).
Note  If you choose transient analysis or AC frequency analysis you can view and modify the parameters of those analyses by clicking on the Set transient options button or the Set AC options button, respectively. This will open another dialog box in which you can change the parameters for the analysis. For information on these dialog box items, see Transient Analysis  and AC Frequency Analysis.


Temperature Sweep Analysis
Analysis/Temperature Sweep

Using temperature sweep analysis, you can quickly verify the operation of your circuit by simulating it at different temperatures. The effect is the same as simulating the circuit several times, once for each different temperature. You control the temperature values by choosing start, end and increment values in the dialog box.

If temperature sweep is not used, the circuit will be simulated at the default temperature of 27°C. (You can change the default temperature from the Global tab of the Analysis Options dialog box.)

Assumptions  See selected analysis (DC operating point, transient, or AC frequency).

To perform the analysis:

1.	Review your circuit and decide on a node for analysis.

2.	Choose Analysis/Temperature Sweep.

3.	Enter or change items in the dialog box.

4.	Click Simulate (press ESC to stop the analysis).

Note  If you choose transient analysis or AC frequency analysis you can view and modify the parameters of those analyses by clicking on the Set transient options button or the Set AC options button respectively.  This will open another dialog box in which you can change the parameters for the analysis.

Viewing the Results

Temperature sweep analysis plots the appropriate curves sequentially. See Viewing the Results in the parameter sweep analysis for an explanation of the number of curves.


Temperature Sweep Analysis Dialog Box
Temperature Sweep Analysis Items Dialog Box

Item	Default	Unit	Notes
Start value	27	°C	Starting temperature for sweep
End value	27	°C	Ending temperature for sweep
Sweep type	Decade	−	Decade/Linear/ Octave
Increment step size	1	°C	For linear sweep type only. Step size for sweep
Output node	A node in your circuit	−	Point in circuit for which you want to see results.
Sweep for:	DC Operating Point	−	DC Operating Point/Transient Analysis/AC Frequency Analysis (See Note)
Note  If you choose transient analysis or AC frequency analysis you can view and modify the parameters of those analyses by clicking on the Set transient options button or the Set AC options button respectively.  This will open another dialog box in which you can change the parameters for the analysis. For information on these dialog box items, see Transient Analysis  and AC Frequency Analysis .


Pole-Zero Analysis
Analysis/Pole-Zero

Pole-zero analysis finds the poles and zeros in the small-signal AC transfer function of a circuit. The analysis begins by calculating the DC operating point and determining the linearized small-signal models for all nonlinear devices. From the resulting circuit, the analysis finds the poles and zeros of the transfer function.

Pole-zero analysis is useful in determining the stability of electronic circuits. Your circuit should have poles with negative real parts; otherwise, your circuit could have an unintentionally large and potentially damaging response to certain frequencies.

The SPICE algorithm used in the pole-zero analysis may occasionally result in an error message such as "Pole-zero iteration limit reached, giving up after 200 iterations." Note that the analysis may still have found all the poles and zeros even if you receive this message.

Assumptions  Analog circuit, small-signal. Digital pins are treated as large resistances to ground.

To perform the analysis:

1.	Review your circuit and decide on input and output nodes (positive and negative). The input nodes are the positive and negative points in the circuit which are the transfer function inputs. Likewise, the output nodes are the positive and negative points in the circuit which are the transfer function outputs. You can use 0 (ground) for both positive nodes or both negative nodes.

2.	Choose Analysis/Pole-Zero.

3.	Enter or change items in the dialog box.

4.	Click Simulate (press ESC to stop the analysis).

Viewing the Results

Pole-zero analysis produces a chart of the real and imaginary coordinates of the poles and/or zeros, depending on which analyses are enabled.


Pole-Zero Analysis Dialog Box
Pole-Zero Analysis Dialog Box Items

Item	Default	Unit	Notes
Analysis type	Gain Analysis	−	Choose one of:  • Gain Analysis (output voltage/input voltage) • Impedance Analysis (output voltage/input current) • Input impedance   (voltage/current as seen from the input terminals) • Output impedance  (voltage/current as seen from the output terminals)
+ input node	A node in your circuit	−	Choose input nodes on opposite sides of the input.
- input node	A node in your circuit	−	Choose input nodes on opposite sides of the input.
+ output node	A node in your circuit	−	Choose output nodes on opposite sides of the output.
- output node	A node in your circuit	−	Choose output nodes on opposite sides of the output.
Pole analysis	Enabled	−	Finds poles of transfer function.
Zero analysis	Enabled	−	Finds zeros of transfer function.


Transfer Function Analysis
Analysis/Transfer Function

Transfer function analysis calculates the DC small-signal transfer function between an input source and two output nodes (for voltage) or an output variable (for current) in a circuit. It also calculates input and output resistances. Any nonlinear models are first linearized based on the DC operating point and then small-signal analysis is performed. The output variable can be any node voltage, while the input must be an independent source defined somewhere in the circuit.

Assumptions  Analog circuit, linear models. Models are linearized.

To perform the analysis:

1.	Review your circuit and decide on an output node, a reference node and an input source.

2.	Choose Analysis/Transfer Function.

3.	Enter or change items in the dialog box.

4.	Click Simulate (press ESC to stop the analysis).

Viewing the Results

Transfer function analysis produces a chart showing the transfer function (output/input), input resistance at the input source and output resistance across the output voltage nodes or at the output variable.


Transfer Function Analysis Dialog Box
Transfer Function Analysis Dialog Box Items

Item	Default	Unit	Notes
Voltage/Current	Voltage		Choose one of Voltage/Current.
Output node	A node in your circuit		For Voltage only, point in circuit for which you want to see results.
Output reference	0 (ground)		For Voltage only, reference voltage.
Output variable	A source in your circuit		For Current only, must be a source in the circuit.
Input source	A source in your circuit		Choose a voltage or current source.


Sensitivity Analysis
Analysis/Sensitivity

Sensitivity analyses calculate the sensitivity of an output node voltage or current with respect to the parameter(s) of all components (DC sensitivity) or one component (AC sensitivity) in your circuit. Both analyses calculate the change produced in an output voltage or current by perturbing each parameter independently and then sending the results to a table.

For DC sensitivity analysis, a DC analysis is first performed to determine the DC operating point of the circuit, then the sensitivity analysis is done. For AC analysis, the AC small-signal sensitivity is calculated.

Assumptions  Analog circuit, small-signal. Models are linearized.

To perform the analysis:

1.	Review your circuit and decide on an output voltage or current. For an output voltage, choose nodes on either side of the circuit output. For an output current, choose a source.

2.	Choose Analysis/Sensitivity.

3.	Enter or change items in the dialog box.

4.	Click Simulate (press ESC to stop the analysis).

Viewing the Results

Sensitivity analyses produce a chart that displays the relevant parameters with their original values and their sensitivities. Sensitivity is expressed as change in output per unit change of input both in values and percentages.


Sensitivity Analysis Dialog Box
Sensitivity Analysis Dialog Box Items

Item	Default	Unit	Notes
Voltage/Current	Voltage	−	Choose one of Voltage/Current.
Output node	A node in your circuit	−	For Voltage only, point in circuit  for which you want to see results.
Reference node	0 (ground)	−	For Voltage only, reference voltage.
Output source	A source in your circuit	−	For Current only, must be a source in the circuit.
DC Sensitivity/  AC Sensitivity	DC Sensitivity	−	When you choose AC sensitivity, you can change AC frequency analysis items.
Component	A component in your circuit	−	For AC sensitivity only, the analysis measures the sensitivity  of the voltage or current relative to the parameter(s) of the component you choose.


Worst Case Analysis
Analysis/Worst Case

Worst case analysis is a statistical analysis that lets you explore the worst possible effects on circuit performance of variations in component parameters.

The first simulation is performed with nominal values. Then, a sensitivity run (AC or DC) is performed. This allows the simulator to calculate the sensitivity of the output waveform with respect to each parameter. Once all the sensitivities have been obtained, a final run provides the worst case analysis result.

Collating Functions

Data from the worst case simulation is gathered by collating functions. A collating function acts as a highly selective filter by allowing only one datum to be collected per run.

The six collating functions are:

This collating function . . .	Captures . . .
Maximum voltage	the values of the Y-axis maxima.
Minimum voltage	the values of the Y-axis minima.
Frequency at maximum	the X value where the Y-axis maxima occurred.
Frequency at minimum	the X value where the Y-axis minima occurred.
Rising edge frequency	the X value the first time the Y value rises above the user-specified threshold.
Falling edge frequency	the X value the first time the Y value falls below the user-specified threshold.

Assumptions  Analog circuit, DC and small-signal. Models are linearized.

To perform the analysis:

1.	Review your circuit and decide on an output node.

2.	Choose Analysis/Worst Case.

3.	Enter or change items in the dialog box.

4.	Click Simulate (press ESC to stop the analysis).

Viewing the Results

Results of the worst case analysis are output in a chart that appears when the analysis is finished. The chart displays DC or AC response of the circuit for each run.


Worst Case Analysis Dialog Box

Item	Default	Unit	Notes
Tolerance	5	%	The analysis varies the parameter by this value.
Collating function	Max. voltage	−	See list above.  When you choose DC Operating Point, only Max.voltage and Min. voltage are valid. Note  If you choose AC frequency analysis, you can view and modify analysis parameters by clicking on the Set AC options button. This will open another dialog box in which you can change the parameters for  the analysis.
Output node	A node in your circuit	−	For voltage only, point in your circuit  for which you want to see results.
Sweep for:	DC operating point	−	DC Operating Point/AC Frequency Analysis.


Monte Carlo Analysis
Analysis/Monte Carlo

Monte Carlo analysis is a statistical analysis that lets you explore how changing component properties affects circuit performance. Multiple simulations are performed and, for each simulation, the component parameters are randomly varied according to the distribution type and parameter tolerance that you set in the dialog box.

The first simulation is always performed with nominal values.  For the rest of the simulations, a delta value is randomly added to or subtracted from the nominal value. The probability of adding a particular delta value depends on the probability distribution. Two probability distributions are available:

Uniform is a linear distribution that generates delta values uniformly within the tolerance range. Any value in the tolerance range is equally likely to be chosen.

Gaussian distribution is generated with the following probability function:

where

u	=  the nominal parameter value

σ	=  the standard deviation value

x	=  the independent variable

The standard deviation, s, is calculated from the parameter tolerance according to:

The percentage of the population included in the tolerance band is determined by a component's nominal parameter value plus or minus σ times the number of standard deviations, SD, in the tolerance band. SD is related to the percentage of population included as shown:

SD	Percentage of Population Included

1.0	68.0

1.96	95.0

2.0	95.5

2.58	99.0

3.0	99.7

3.29	99.9

For example, if you set the tolerance percentage to 5%, then, for a
1 kΩ resistor in your circuit, σ is 50 Ω. One standard deviation leads to a tolerance band of 0.95 kΩ to 1.05 kΩ (1 kΩ +/- 50 Ω), and 68.0% of the population is included. At 1.96 standard deviations, the tolerance band is 0.902 kΩ to 1.098 kΩ (1 kΩ +/- 98 Ω), and 95.0% of the population is included.

Note that the tolerance percentage is applied globally to all components.

Assumptions  See selected analysis (DC operating point, transient or AC frequency).

To perform the analysis:

1.	Review your circuit and decide on an output node.

2.	Choose Analysis/Monte Carlo.

3.	Enter or change items in the dialog box.

4.	Click Simulate (press ESC to stop the analysis).

Note  If you choose transient analysis or AC frequency analysis, you can view and modify the parameters for those analyses by clicking on the Set transient options button or the Set AC options button, respectively.  This will open another dialog box in which you can change the parameters for the analysis.

Viewing the Results

Monte Carlo analysis plots the appropriate voltage curves sequentially. The number of curves is equal to the number of runs you specified in the dialog box.


Monte Carlo Analysis Dialog Box
Monte Carlo Analysis Dialog Box Items

Item	Default	Unit	Notes
Number of runs	2	−	Must be greater than or equal to 2.
Tolerance	5%	−	This is the maximum variation for uniform distribution, or the percentage of a standard distribution for Gaussian.
Seed	0	−	Used to initiate random number generator.
Distribution type	Uniform	−	Uniform/Gaussian.
Output node	A node in your circuit	−	Point in circuit for which you want to see results.
Sweep for:	Transient	−	DC Operating Point/Transient Analysis/ AC Frequency Analysis.


Graphs Command
Analysis/Graphs

The analysis graphs window is a multipurpose display tool that lets you view, adjust and save graphs and charts. It is used to display the results of all Electronics Workbench analyses in graphs and charts; a graph of oscilloscope traces and Bode plots; an error log chart where you can view any error or warning messages generated during simulation; a chart of simulation statistics (when you set Print statistical data to ON in the Transient tab of the Analysis/Analysis Options dialog box).

The display shows both graphs and charts. In a graph, data are displayed as one or more traces along vertical and horizontal axes. In a chart, text data are displayed in rows and columns. The Analysis Graphs window is made up of several tabbed pages.

Activating and Closing the Window

Viewing Pages

Viewing Graphs

Viewing Charts

Cut, Copy and Paste

New, Open and Save

Print and Print Preview


Activating and Closing the Analysis Graphs Window

The Analysis Graphs window appears automatically when you perform an analysis.

To activate the window, do one of the following:

Click Simulate in any of the analyses' dialog boxes, or

Choose Analysis/DC Operating Point (for DC operating point analysis there is no dialog box, so the window appears when the analysis has finished), or

Choose Analysis/Display Graphs, or

Click the Display Graphs button .

When the window is on the screen, it remains visible until you do one of the following:

Close the window, or

Choose Analysis/Display Graphs.


Viewing Pages in the Analysis Graphs Window

Every analysis you perform on a circuit displays its results on a separate page.

 To view a page, click its tab.

 To scroll through pages (when there are too many tabs to fit in the available space), click the forward or reverse arrow button that appear at the right edge of the tabs.

 To change page properties:

1.	Select a page by clicking its tab.

2.	Click the Properties button. The Page Properties dialog box appears.

To change:	Do this:
Name of the tab	modify Tab Name field
Title of chart or graph	modify Title field
Title's font	click Font button
Background color of page	click Color button


Viewing Graphs

To help you examine graphical data, you can use a grid, a legend and vertical cursors. You can also zoom in on any part of a graph. You can apply these tools separately or together. In addition, you can change several graph display characteristics from the tabs of  the Graph Properties dialog box.

Note  To display the Graph Properties dialog box or to use the buttons described in this section, you must have a graph selected. If the Page Properties dialog box appears, you have a page selected rather than a graph. Click on a graph to select it. A red arrow appears to the left of the graph to indicate it is selected.

Note  The Graph Properties dialog box allows you to choose either OK or Apply. Clicking OK applies the change and closes the dialog box. Clicking Apply applies the change and leaves the dialog box open for additional selections.

Grid

Legend

Cursors

Zoom and Restore

Title

Axes

Traces


Grid (Viewing Graphs)

 To apply a grid to a graph:

1.	Select a graph by clicking anywhere on it.

2.	Click the Toggle Grid button. To remove the grid, click the button again, or

2.	Click the Properties button. The Graph Properties dialog box appears.

3.	Choose the General tab.

4.	Enable the Grid On option. If desired, change the grid pen size and color.


Legend (Viewing Graphs)

 To apply a legend to a graph:

1.	Select a graph by clicking anywhere on it.

2.	Click the Toggle Legend button. To remove the legend, click the button again, or

2.	Click the Properties button. The Graph Properties dialog box appears.

3.	Select the Global tab.

4. 	Enable the Legend On option. If desired, change the labels of the traces using the Traces tab.


Cursors (Viewing Graphs)

When you activate the cursors, two vertical cursors appear on the selected graph. At the same time, a window pops up that displays a list of data for one or all traces.

The cursor data includes:

x1,y1	(x,y) co-ordinates for the left cursor
x2,y2	(x,y) co-ordinates for the right cursor
dx	x-axis delta between the two cursors
dy	y-axis delta between the two cursors
1/dx	reciprocal of the x-axis delta
1/dy	reciprocal of the y-axis delta
min x, min y	x and y minima within the graph ranges
max x, max y	x and y maxima within the graph ranges
 To activate the cursors:

1.	Select a graph by clicking anywhere on it.

2.	Click the Toggle Cursors button . To remove the cursors, click the button again.

or

2.	Click the Properties button. The Graph Properties dialog box appears.

3.	Select the General tab.

4.	Enable the Cursors On option.

5.	Select Single Trace to view cursor data for one trace or All Traces to view cursor data for all traces. If you select Single Trace and there is more than one trace in your graph, use Trace to select the one you want.

 To move a cursor, click and drag it horizontally.


Zoom and Restore (Viewing Graphs)

 To zoom in on any part of a graph:

1.	Select a graph by clicking anywhere on it.

2.	Click and drag the pointer until the dotted enlargement box covers the region of the graph that you want to zoom in on.

3.	Release the mouse button. The axes are scaled and the graph redrawn based on the enlargement box, or

2.	Click the Properties button. The Graph Properties dialog box appears.

3.	Choose an axis tab to zoom along that axis. For example, choose the Bottom Axis tab to zoom along the horizontal dimension. (Check the Traces tab to see which axis is used for the range you want to zoom.)

4.	Type a new minimum and maximum.

 To restore a graph to its original scale, click the Restore button .


Title (Viewing Graphs)

 To apply a title to a graph:

1.	Select a graph by clicking anywhere on it.

2.	Click the Properties button. The Graph Properties dialog box appears.

3.	Choose the Global tab.

4.	Type a new title. To change the title's font, click the Font button.


Axes (Viewing Graphs)

You can change several characteristics of a graph's axes from the four axes tabs in the Graph Properties dialog box. The options are identical in each of the tabs.

 To change the characteristics of an axis:

1.	Select a graph by clicking anywhere on it.

2.	Click the Properties button. The Graph Properties dialog box appears.

3.	Select the axis tab for the axis you want to change.

4.	Change any of the axis' characteristics.

When you change the scale on an axis (for example, from linear to logarithmic), you need to adjust the min and max range and the settings for the divisions or your trace will not look right.

If scale is set to Linear, then the description for divisions is correct. However, if scale is set to Log or Octave, it is misleading. In these cases, Number is the number of tick marks shown per octave/decade. Frequency still indicates how often numbers are displayed.

In the following graph, Scale=Logarithmic, Number=9, Frequency=18 which means there are 9 ticks per decade and every 18 ticks a value is displayed on the axis.


Traces (Viewing Graphs)

You can change several characteristics of each trace in a graph from the Traces tab in the Graph Properties dialog box.

 To change the characteristics of a trace:

1.	Select a graph by clicking anywhere on it.

2.	Click the Properties button. The Graph Properties dialog box appears.

3.	Choose the Trace tab.

4.	Select a trace.

5. 	Change any of the trace's characteristics.


Viewing Charts

To help you examine and organize a chart, you can sort rows, adjust column widths, change precision and add a title.

 To sort a row of data, click the column name button of the column you want to sort by. Sorting order is from low to high for numbers, otherwise, it is alphabetical.

 To adjust the width of a column, click and drag the left edge of the column name button.

 To change the chart's column precision (number of significant digits) or title:

1.	Select a chart by clicking anywhere on it.

2.	Click the Properties button. The Chart Properties dialog box appears.

3.	To change the chart title, type a new title. To change the font, click the Font button.

4.	To change a column's precision, select a column number and a precision (number of significant digits). Precision only affects columns that contain numerical values.

5.	Click OK.


Cut, Copy and Paste (Analysis Graphs window)

The Analysis Graphs window lets you cut, copy and paste pages, graphs and charts.

Note  You must use the cut, copy and paste buttons from this window. You cannot use the Electronics Workbench menus, buttons and keyboard shortcuts for these functions.

 To cut, copy and paste pages:

1.	Select a page by clicking on its tab.

2.	Click the cut or copy button.

3.	Click the paste button. The cut or copied page appears.

Note  When a page is selected (the red arrow points to the tab), cut, copy and paste affect page properties only. They do not affect the graphs or charts on the page.

 To cut, copy and paste graphs and charts:

1.	Select a graph or chart.

2.	Click the Cut or Copy button.

3.	Click the Paste button to paste the graph or chart onto the same page.

or, to paste onto a new page:

3.	Click the New button.

4.	Choose New Page.

5.	Type a tab name and click OK.

6.	Click the Paste button.

Note  When a graph or chart is selected (the red arrow points to the graph or chart), cut, copy and paste affect the selected graph or chart only. They do not affect overall page properties.


New, Open and Save (Analysis Graphs window)

 To open a new page, click the New button and choose New Page.

 To delete all pages, click the New button and choose Delete All Pages.

 To open an existing graph file:

1.	Click the Open button. A file browser appears.

2.	Select the file you want to open. Graph files have the file extension .GRA.

3.	Click Open.

 To save a graph file:

1.	Click the Save button. A file browser appears.

2.	Select a file you want to overwrite or type a new filename. Graph files have the file extension .GRA. The file extension is automatically added.

3.	Click Save.

Note  Filenames must have a maximum of eight characters and cannot contain spaces.


Print and Print Preview (Analysis Graphs window)

 To view the printed pages before you print:

1.	Click the Print Preview button. One or two pages appear in the window.

2.	Use Next Page and Prev Page to scroll through the pages.

3.	Use One Page/Two Page to toggle between viewing one or two pages at a time.

4.	Use Zoom In, Zoom Out to control the zoom on the page(s).

5.	Click Print to open the print dialog box and print the pages.

or

5.	Click Close to close print preview.

 To print pages:

1.	Click the Print button on the toolbar or from the print preview. The print dialog box appears.

2.	If desired, select Print to file.

3.	Choose a print range.

4.	Choose the number of copies.

5.	Enable Collate if required.

6.	Click OK.


About Nodes

Nodes are areas of a circuit that share a common reference point. They may or may not be displayed, depending on the options selected on the Show/Hide tab of the Circuit/Schematic Options dialog box. Nodes are identified with a square label.

To change the properties of a node (color and initial settings), double-click its square label to display its Component Properties dialog box.

To change the color of the wires of a node, double-click the wire, choose the Schematic Options tab, click the Color button and choose the color you want.

Note  Node color overrides color set for any of its individual wires.


Analog ICs Parts Bin

3-Terminal Opamp

5-Terminal Opamp

7-Terminal Opamp

9-Terminal Opamp

Comparator

Phase-Locked Loop


3-Terminal and 5-Terminal Opamp

An opamp (operational amplifier) has a very high voltage gain and input impedance, a very low output impedance and a high bandwidth.

The "+" terminal is non-inverting, the "-" terminal is inverting.

The parts bin contains both a 3-terminal and a 5-terminal opamp. The 3-terminal opamp simulates much faster, but since the model is not as complex, it does not model all the characteristics of an opamp, for example positive feedback.

The 5-terminal opamp has two extra terminals (i.e. the positive and negative power supply terminals) at the top and bottom respectively and is based on the Boyle-Cohn-Pederson model. It models some second-order effects like common-mode rejection and output voltage and current limiting.

See also:

Ideal Opamp Model


Opamp: Background Information

The operational amplifier is a high-gain block based upon the principle of a differential amplifier. It is common to applications dealing with very small input signals.

The open-loop voltage gain (A) is typically very large (10e+5 to 10e+6). If a differential input is applied across the "+" and "-" terminals, the output voltage will be:

    V = A * (V+ - V-)

The differential input must be kept small, since the opamp saturates for larger signals. The output voltage will not exceed the value of the positive and negative power supplies (Vp), also called the rails, which vary typically from 5 V to 15 V. This property is used in a Schmitt trigger, which sets off an alarm when a signal exceeds a certain value.

Other properties of the opamp include a high input resistance (Ri) and a very small output resistance (Ro). Large input resistance is important so that the opamp does not place a load on the input signal source. Due to this characteristic, opamps are often used as front-end buffers to isolate circuitry from critical signal sources.

Opamps are also used in feedback circuits, comparators, integrators, differentiators, summers, oscillators and wave-shapers. With the correct combination of resistors, both inverting and non-inverting amplifiers of any desired voltage gain can be constructed.


Ideal Opamp Model

The ideal opamp model is the fastest to simulate. Its characteristics include:

infinite open-loop voltage gain (A),

infinite input resistance (Ri),

zero output resistance (Ro),

infinite bandwidth,

differential input voltage of zero, so V- = V+,

    and

zero current flow into either input terminal.


Opamp Model Parameters

An opamp is primarily defined by the following:

Voltage gain: the ratio of the output voltage to the voltage difference at the input terminals.

Input offset voltage: the offset voltage required at the input to produce a zero output.

Input offset current: the difference of the base currents of the input transistors in a non-ideal (unmatched) transistor opamp.

Slew rate: the rate of change of output voltage in response to a step input.

Unity-gain bandwidth: the frequency at which the open-loop voltage gain equals 1.


Comparator

A comparator is a circuit that compares two input voltages and produces an output in either of two states, indicating the greater than or less than relationship of the inputs.

A comparator switches to one state when the input reaches the upper trigger point. It switches back to the other state when the input falls below the lower trigger point.

A voltage comparator may be implemented with any op-amp, with consideration for operating frequencies and slew rate, or with speciallized ICs such as the LM339.

The comparator compares a reference voltage, fixed or variable, with an input waveform.

If the input is applied to the non-inverting input and the reference to the inverting input (lower circuit), the comparator will be operating in the non-inverting mode. In this case, when the input voltage is equal to (or slightly less than) the reference voltage the output will be at its lowest limit (near the negative supply) and when the input is equal to (or slightly greater than) the reference voltage the output will change to its highest value (near the positive supply).

If the inverting and non-inverting terminals are reversed (upper circuit) the comparator will operate in the inverting mode.

In the example shown below, the input is a  6v peak triangle waveform and the comparison reference is 4VDC.

In the lower circuit (non-inverting), when the input is below the reference (4V) the output is at 0.1V (lowest value) and in the upper (inverting) circuit the output is at +3.5V (highest).

As the input "crosses", or becomes greater than 4V, the outputs change state.

Changing input amplitude changes the time the outputs are high or low. This device characteristic may be utilized to produce variable width pulses or a form of Pulse Width Modulation.


7-Terminal and 9-Terminal Opamp

These opamps use external netlists for simulation. For information on importing netlists, see Importing and Exporting Netlists.

See also:

7-Terminal Opamp Example

9-Terminal Opamp Example

Ideal Opamp Model

Opamp Model Parameters


7-Terminal Opamp Example

Analog Devices AD705 picoamp input current bipolar Op-Amp.

To achieve frequency compensation for this circuit, add a suitable value capacitor from the COMP terminal to ground.

The example circuit shown below, with no frequency compensation,  provides a gain of approximately 10dB below 15kHz. and has a -3dB rolloff at approximately 92kHz and -10dB at 890kHz.

A 200 pF frequency compensating capacitor reduced the -3dB frequency ( first pole) to 57 Khz.


9-Terminal Opamp Example
9-Terminal Opamp

CLC431 9-Terminal Wide Band Opamp.

The CLC431 is a very versatile wide band opamp designed for the bandwidths required for video and high speed communications applications.

In the example shown below, the device is operating in the non-inverting mode as a video amplifier with a voltage gain of  2 (6 dB). In this configuration the -3dB bandwidth (first pole frequency) is 65 MHz.

Special enable/disable control functions are available to allow video multiplexing and switching. Check with manufacturer's specs for more information and applications.


Phase-Locked Loop

This component models the behavior of a phase-locked loop circuit, which is a circuit that contains an oscillator whose output phase and frequency are steered to keep it synchronized with an input reference signal.

A phase-locked loop circuit is composed of three functional blocks: a phase detector, a low-pass filter and a voltage-controlled oscillator (VCO). The phase detector behaves as an analog multiplier. It outputs a DC voltage which is a function of the phase difference between the input reference signal and the VCO output signal. The output of the phase detector is input to the low-pass filter, which removes the high-frequency noise and outputs a DC voltage. The VCO converts the DC voltage into its corresponding frequency signal.

PLL parameters, which may be set to the desired design values, include:  phase detector conversion gain, VCO conversion gain, VCO free running frequency, loop filter pole frequency and VCO output amplitude.

In the example circuit shown below, parameters are set to illustrate extreme system overshoot (long settling time). In most systems, such overshoot would be totally unacceptable and further design and evaluation would be necessary.

The switch, activated by the space bar, produces a step change of frequency.

Response of the loop filter (error voltage to the VCO) and VCO output may be monitored. Swings in the VCO frequency, as the system settles, appears on the scope because of the extreme overshoot deliberately introduced in this example.

To improve system performance, change the loop filter pole frequency to 2 Hz. and then to 10 Hz. (Modify the FP (first pole) value in the Value tab of Circuit/ Component Properties.)


Basic Parts Bin

Connector

Resistor

Capacitor

Inductor

Transformer

Relay

Switch

Time-Delay Switch

Voltage-Controlled Switch

Current-Controlled Switch

Pull-up Resistor

Potentiometer

Resistor Pack

Voltage-Controlled Analog Switch

Polarized Capacitor

Variable Capacitor

Variable Inductor

Coreless Coil

Magnetic Core

Nonlinear Transformer


Connector

The round dot in the Basic parts bin is a connector. Use it to join wires in a circuit. A connector has four terminals, one on each side. It can join up to four wires.

Connectors are created automatically when you stretch a wire so that it touches another wire.

When connectors are not needed, they disappear automatically. Permanent connectors can be created by assigning a label to them.


Resistor

A  resistor's resistance is measured in ohms. It can have any value from Ω to kΩ.

The Resistance, R, of a resistor instance is calculated using the following equation:

R = Ro * { 1 + TC1*(T - To) + TC2*[(T-To)^2] }

where:

R   == The resistance of the resistor

Ro  == The resistance of the resistor at temperature To

To  == Normal temperature == 27 degrees C  [CONSTANT]

TC1 == First order temperature coefficient

TC2 == Second order temperature coefficient

T   == Temperature of the resistor

All of the above variables can be modified, with the exception of To, which is a constant.

Note that Ro is the resistance specified on the Value tab of the resistor properties dialog, not "R".

T can be specified in two ways:

1. Select the "Use global temperature" option on the Analysis Setup tab of the resistor properties dialog box. Specify the (Global) "Simulation temperature (TEMP)" on the Analysis Options dialog box.

2. Deselect the "Use global temperature" option on the Analysis Setup tab of the resistor properties dialog box. Specify the local temperature of the resistor instance on the Analysis Setup tab of the resistor properties dialog.

The resistor is ideal, with the temperature co-efficient set to zero. To include resistors in the Temperature Analysis, set the temperature co-efficient "TC1 and TC2" in the resistor properties dialog box.

See also:  Potentiometer


Capacitor

A capacitor  storeselectric energy in the form of an electrostatic field. It affects AC relative to capacitance and frequency and DC depending on capacitance alone.

Its capacitance, measured in farads, can be any value from pF to mF.

See also:    Variable Capacitor


Inductor

An inductor storesenergy in an electromagnetic field created by changes in current flowing through it. Its ability to oppose a change in current flow is called inductance (L), which is measured in henrys.

It can have any value from µH to H.

See also:    Variable Inductor


Transformer

Transformers are one of the most common and useful applications of inductance. They can step up or step down an input primary voltage (V1) to a secondary voltage (V2). The relationship is given by V1/V2 = n, where n is the ratio of the primary turns to the secondary turns.

The parameter n can be adjusted by editing the transformer's model.

To properly simulate the transformer, both sides must have a common reference point, which may be ground.


Relay

The magnetic relay is a coil with a specified inductance (Lc, in henries) that causes a contact to open or close when a specified current (Ion, in A) charges it.

The contact remains in the same position until the current falls below the holding value (Ihd, in A), at which point it returns to its original position.


Switch

The single-pole, double-throw switch can be closed or opened (turned on or off) by pressing a key on the keyboard.

You specify the key that controls the switch  by typing its name in the Value tab of the Circuit/Component Properties dialog box. For example, if you want the switch to close or open when the spacebar is pressed, type space in the Value tab, then click OK.

To use...	Type...

Spacebar	space

ENTER	ENTER

letters a to z	the letter (e.g. a)

numbers 0 to 9	the number (e.g. 1)


Time-Delay Switch

The time-delay switch has two values, time on (Ton) and time off (Toff). It has an infinitely high resistance at Toff (when the switch is open) and an infinitely low resistance at Ton (when the switch is closed).

Ton cannot be equal to Toff. Both values must be greater than zero.


Voltage-Controlled Switch

The voltage-controlled switch  has two values, turn-on voltage (Von) and turn-off voltage (Voff). It closes when the voltage across the controlling terminals is equal to or greater than the parameter Von. It opens when the voltage is equal to or less than Voff.

Voltage-controlled switches can be used to model digital gates.


Current-Controlled Switch

The current-controlled switch is similar to the voltage-controlled switch. When the current through the controlling terminals is equal to Ion, the switch closes. When the current equals Ioff, the switch opens. This switch can be used to model digital gates.

See also:   Voltage-Controlled Switch


Pull-Up Resistor

The pull-up resistor has one end connected to Vcc. The other end is connected to a point in a logic circuit that needs to be raised to a voltage level closer to Vcc.


Potentiometer

A potentiometer is much like a regular resistor, except that you can adjust its setting. In the Value tab of the Circuit/Component Properties dialog box, you set the potentiometer's resistance, initial setting (as a percentage) and increment (as a percentage). You also identify the key ("A" to "Z") that you will use to control the setting.

To decrease the potentiometer's setting, press the identified key.

To increase the setting, press and hold SHIFT and press the identified key.

For example, say the potentiometer is set to 45%, the increment is 5% and the key is "R". You press "R", and the setting drops to 40%. You press "R" again, and it drops to 35%. You press SHIFT and "R", and the setting rises to 40%.

See also:   Resistor


Resistor Pack

This component is a package containing eight resistors, side by side. The terminals for each resistor are directly opposite each other.

The values of all resistors are the same and can be set globally by dragging a resistor pack into the circuit window, double-clicking it and entering the value in the Value tab of the dialog box that appears.


Voltage-Controlled Analog Switch

The voltage controlled switch has a function similar to that performed by a mechanical On/Off switch except that the On/Off conditions are selected by a control voltage.

When the control voltage is below a selected value, the switch is off and the input and output signals are disconnected.

When the control voltage is above the selected value, the switch is on and the input and output signals are connected.

In the example shown below, the analog switch is used to periodically sample a sine wave input signal (lower waveform on the display) at intervals determined when the control signal is high, above 4.9V for this model. When the control voltage drops below 4.8V the switch is turned off and the output drops to zero.

The sampled waveform at the output is the upper waveform on the display. Inputs may be any waveshape and any (reasonable) values. This type of sampling is utilized in time division multiplex systems.

Observe the CONTROL (switching) waveform and the output to confirm switching operation.

Sampling rate may be changed by changing the frequency of the CLOCK generator.

An example of an IC performing this function is the MC14016, a 14 pin IC which includes four individual analog switches with individual switching control inputs.


Polarized Capacitor

The polarized capacitor must be connected with the right polarity. Otherwise, an error message will appear.

Its capacitance, measured in farads, can be any  value from pF to mF.


Variable Capacitor

The variable capacitor is simulated as an open circuit with a current across the capacitor forced to zero by a large impedance value.

Values are set in the same way as those for the potentiometer.

See also:    Potentiometer


Variable Inductor

This component acts much like a regular inductor, except that its setting can be adjusted.

The variable inductor is simulated as an open circuit with a current across the inductor forced to zero by a large impedance value.

Values are set in the same way as for the potentiometer.

See also:    Potentiometer


Coreless Coil

This component is a conceptual model that you can use as a building block to create a wide variety of inductive and magnetic circuit models. Typically, you would use the coreless coil together with the magnetic core to build up systems that mock the behavior of linear and nonlinear magnetic components. Output is in the form of a voltage proportional to the product of input current and number of turns, and represents the magnetomotive force (mmf) which is  produced. The output voltage behaves like a magnetomotive force in a magnetic circuit, that is, when the coreless coil is connected to the magnetic core or some other resistive device, a current flows.

Vo = N * I in

In the sample circuit shown below, the number of turns (N) is set at 10 and the input current at 0.707A (RMS). This results in an mmf represented by  7.07  v (RMS)

Applications for this component usually involve modeling an mmf is applied to a magnetic circuit or component.

The coreless coil may be used to provide excitation field to the magnetic core. These two components provide for a wide scope in the modeling and design of linear and non-linear magnetic components.

See also:    Magnetic Core


Magnetic Core

This component is a conceptual model that you can use as a building block to create a wide variety of inductive and magnetic circuit models. It  may be used in a wide variety of linear and non-linear magnetic component designs. Typically, you would use the magnetic core together with the coreless coil to build up systems that mock the behavior of linear and nonlinear magnetic components. The two magnetic modeling components are combined in the nonlinear transformer. It takes as input a voltage which it treats as a magnetomotive force (mmf) value. This input voltage, in many cases, would be obtained from the coreless coil.

Core dimensions (length and cross sectional area) are taken into account. Up to 15 co-ordinates in terms of amp turns/meter and webers per square metre are combined to produce the output.

Output is a current representing the back EMF produced in the overall magnetic circuit,

Definition of the (up to 15 pairs) of co-ordinates allow for modeling of the linear or non-linear magnetic performance.

In the simple example shown below, all parameters are set to unity (area=1 sq. mtr., length=1M, and only one co-ordinate pair is entered).

The output current is converted to a voltage by current to the voltage component (basically used as a current probe).

See also:    Coreless Coil


Nonlinear Transformer

This component is based on a general model that can be customized for different applications.

It is implemented using a magnetic core and coreless coil as building blocks, together with resistors and inductors. Using this transformer, you can model physical effects such as nonlinear magnetic saturation, primary and secondary winding losses, primary and secondary leakage inductances, and core geometric size.

See also:    Magnetic Core and Coreless Coil


Capacitor: Background Information

Capacitors in an AC circuit behave as "short circuits" to AC signals. They are widely used to filter or remove AC signals from a variety of circuits--AC ripple in DC power supplies, AC noise from computer circuits, etc.

Capacitors prevent the flow of direct current in a DC circuit. They can be used to block the flow of DC, while allowing AC signals to pass. Using capacitors to couple one circuit to another is a common practice.

Capacitors take a predictable time to charge and discharge and can be used in a variety of time-delay circuits. They are similar to inductors and are often used with them for this purpose.

The basic construction of all capacitors involves two metal plates separated by an insulator. Electric current cannot flow through the insulator, so more electrons pile up on one plate than the other. The result is a difference in voltage level from one plate to the other.

See also:   Inductor


Inductor: Background Information

An inductor is a coil of wire of one "turn" or more. It reacts to being placed in a changing magnetic field by developing an "induced" voltage across the turns of the inductance, and will provide current to a load across the inductance. Voltages can be very large.

Inductors, like capacitors, store energy in electric fields. Their "charge" and "discharge" times make them useful in time-delay circuits.

Electric transformers take advantage of the transfer of energy in a magnetic field from the primary winding to the secondary winding, using induced voltage and current. The transfer is proportional to the ratio of the winding turns.

Radio antennae are inductors that operate like transformers in generating and detecting electromagnetic fields. Their efficiency is proportional to their size.

The ignition coil in an automobile develops a very high induced voltage when the current through it suddenly becomes very great. This is the voltage that fires spark plugs.


About Resistance

Ohm's law states that current flow depends on circuit resistance:

    I = E/R

Circuit resistance can be calculated from the current flow and the voltage:

    R = E/I

Circuit resistance can be increased by connecting resistors in series:

    R = R1 + R2 +...+ Rn

Circuit resistance can be reduced by placing one resistor in parallel with another:

                 1

    R =  -----------------

           1     1     1

          --- + --- + ---

           R1    R2    R3


Resistor: Background Information

Resistors come in a variety of sizes, related to the power they can safely dissipate. Color-coded stripes on a real-world resistor specify its resistance and tolerance. Larger resistors have these specifications printed on them.

Any electrical wire has resistance, depending on its material, diameter and length. Wires that must conduct very heavy currents (ground wires on lightning rods, for example) have large diameters to reduce resistance.

The power dissipated by a resistive circuit carrying electric current is in the form of heat. Circuits dissipating excessive energy will literally burn up. Practical circuits must take power capacity into account.


About Switches

Switches are resistive elements that are either open or closed. Four controlled switches are included in the parts bin:

Switch

Time-Delay Switch

Voltage-Controlled Switch

Current-Controlled Switch

The relay can also be used as a switch.


Current: Background Information

Current is calculated as:

    I = E/R

Alternating or direct current comes from a power supply to a load, where the output voltage of the supply is not important (and may, in fact, be very low).

Most modern DC power supplies, using electronic control of the output level, can be used as either voltage sources or current sources. When the load on the power supply becomes very heavy (a small load resistance) these supplies will switch from a voltage supply to a current supply.

Bipolar transistors are current-based. They can be treated as low impedance current sources for circuit analysis purposes.

Current sources are often used as signal sources during the analysis of electric networks if there is more concern about the currents flowing into and out of a point than about the voltage appearing across a component.

In general, current sources are associated with low impedance circuits, while voltage sources are associated with high impedance circuits.

AC and DC current sources are provided in the Sources parts bin. You can adjust their values from µA to kA.

See also:

Bipolar transistors

AC Current Source

DC Current Source


Controls

Voltage Differentiator

Voltage Integrator

Voltage Gain Block

Transfer Function Block

Multiplier

Divider

Three-Way Voltage Summer

Voltage Limiter

Voltage-Controlled Limiter

Current Limiter Block

Voltage Hysteresis

Voltage Slew Rate


Voltage Differentiator

This component calculates the derivative of the input voltage (the transfer function, s) and delivers it to the output. It is used in control systems and analog computing applications.

Differentiation may be described as a "rate of change" function and defines the slope of a curve.

Rate of change = dV/dT

Investigations

Sine wave

The slope of a sine wave changes continuously and smoothly. Therefore, the differentiator output should follow the sine shape.

In the example circuit shown below, if you change frequency from 10Hz. to 100Hz., the rate of change of the waveform will increase by a factor of 10. The differentiator output will also increase by the same factor.

When investigating, note also a 90 degree phase shift from input to output.

Triangle waveforms

In an ideal triangle waveform the rising and falling slopes are constant with an abrupt change taking place at the peaks.

Since the rate of change (slope) during rise and fall are constant, the differential result is also constant.

The reversal of slope at the peaks (from rise to fall/fall to rise) produces a large instantaneous change in the differentiator output, resulting in a square wave output.

In the example circuit, as for the sine wave. If you change frequency from 10Hz. to 100Hz., the rate of change of the waveform will increase by a factor of 10. The differentiator output will also increase by the same factor.

Square waves

In an ideal square wave, the change takes place only at the rising and falling edges. The change is instantaneous. This instantaneous rate of change

(dV/dT = dV/0)

will produce an infinitely large output from a differentiator.

Since ideal square or pulse waveforms, as produced by the function generator in Electronics Workbench, have zero rise and fall times, the result of differentiation is infinite (dV/0 = infinity).

In the example circuit, outputs from the differentiator are limited to +/-5 kilo volts. With the ideal square wave input, the differentiator output will be seen to be +/-5kV.

All real square wave and pulse signals have finite rise times, however small.

To introduce finite rise and fall times into the input to the differentiator, in order to investigate realistic situations, use an RC network placed in series with the function generator.

Note    Since the rise and fall times are fixed, the differentiator output does not change with change of input frequency as for the sine and triangle waveforms.

Changing the RC time constant and comparing differentiator output will illustrate this point.


Voltage Integrator

This component calculates the integral of the voltage (the transfer function, 1/s) and delivers it to the output. It is used in control systems and analog computing applications.

The true integrator function continously adds the area under a curve for a specified time interval.

For waveforms that are symmetrical about the zero axis, area above and below the axis is  zero and the resulting integrator output is zero.

For waveforms that are not symmetrical about the zero axis, the "areas" will be different. If area above the axis is greater, integrator output will rise. If area is less, integrator output will fall.

Investigations

1. 	In the initial circuit, the input signal is symmetrical (+/- 5V) about the zero axis and the integrator output is zero for sine, square and triangle waveforms.

2. 	To make the waveforms unsymmetrical about the zero axis use the OFFSET control on the function generator. Setting the OFFSET equal to the AMPLITUDE setting will reference the input to ground (0V).

In this case, the output is always positive. When output is high, "area" is continually added. Output will rise indefinitely.

Changing frequency changes the area. Therefore, in the case of lower frequencies, output rises faster.


Voltage Gain Block

This component multiplies the input voltage by the gain and delivers it to the output. This represents a voltage amplifier function with the gain factor, K, selectable with the Value tab of Circuit/Component Properties. The voltage gain block is used in control systems and analog computing applications.

In the example shown below, the input is a 0.707v RMS (2v peak to peak) sine wave and the gain factor K is set at 5.  The output then is K times the input.

 (.707*5= 3.535v RMS  or 10 v peak to peak)

CAUTION   Using the default model, as in this example, sine wave inputs may be any value.

Suitable settings of model parameters will allow for virtually unlimited flexibility for practical applications.


Transfer Function Block

This component models the transfer characteristic of a device, circuit or system in the s domain. The transfer function block is specified as a fraction with polynomial numerators and denominators. A transfer function up to the third order can be directly modeled. This component may be used in DC, AC and transient analyses.

This transfer function model is defined in a form of the rational function:

T(s) =

Transfer functions up to the third order may be modeled.

In the example shown below, the transfer function for a simple first order low pass filter is used. Only the numerator and denominator constants A0 and B0 are required in this case. These are equal to two pi times the cutoff frequency (first pole).

The cursor on the Bode Plotter may be used to confirm first order performance with -3dB at 10kHz. and rolloff of 6dB per octave above 20kHz.


Multiplier

This component multiplies two input voltages.

The basic function multiplies the  X and Y inputs.

Vo = Vx * Vy

Gain factors may be applied to the X and Y inputs and to the output.

Examples shown below:

a) Two DC voltages are multiplied  ( 4V * 2V = 8V)

b) Two volts DC multiplied by 2v RMS  (2V * 2v RMS = 4v RMS)

c)  Two AC signals, 2sinx and 4 cosx


Divider

This component divides one voltage by the other.

In basic (default) form the voltage at the Y input is divided by the voltage at the X input.

Vo = Vy/Vx

In the example shown below,  the 120v RMS (339.38v  peak to peak) sine wave at the Y input is divided by a 16.96V DC voltage at the X input. The result is 339.38v (peak to peak) / 16.97V = 20v  peak to peak.

If Vx is replaced with a 12v  RMS voltage, in phase with Vy, the output will be 10V DC.

CAUTION   If the X (denominator) voltage crosses 0v when any voltage is present at the Y (numerator) terminal, the quotient will go to infinity and a large positive or negative "spike" will be observed on the scope.


Three-Way Voltage Summer

This component is a math functional block that receives up to three voltage inputs and delivers an output equal to their arithmetic sum. Gain for all three inputs as well as the summed output may be set to match any three input summing application.

In the example shown below, all gains are set to unity.

The summer may be used to illustrate the result of adding harmonically related sine wave components which make up a complex waveform (the first three terms in the Fourier expression defining the waveform).

In the example, a fundamental frequency of 60 Hz. and the third and fifth harmonics (in phase) may be progressively added to illustrate the basic makeup of a square wave.

Amplitude and phase of any of the signals may be varied to experiment further.

CAUTION    The switches should not be operated while a solution is in progress. This will result in solution error messages. Allow the solution to pause (or pause it by clicking on the solution switch). Operate a switch to add the desired harmonic, and then solve the circuit again.


Voltage Limiter

This is a voltage "clipper". The output voltage excursions are  limited, or clipped, at predetermined upper and lower voltage levels.

In the example shown below, the upper voltage limit is set to +5V and the lower limit is set to - 5 volts. These settings provide symmetrical clipping on the positive and negative peak excursions of the input waveform when these peaks exceed the set limit (clipping) values.

The 10 v RMS (14.14v peak) input is limited at +/-5V.

Note   If the input peak voltages are within the set limiting voltages, the input signal is passed through the limiter circuit undistorted.

Unsymmetrical clipping is selected by setting the limit voltages to different values (ie. +5V and -2V). This technique may be used to produce non-standard waveshapes, starting with sine, triangle sawtooth and other symmetrical waveforms.


Voltage-Controlled Limiter

A voltage "clipper". This component is a single input, single output function. The output voltage excursions are  limited, or clipped, at predetermined upper and lower voltage levels. Output smoothing occurs within the specified range. The voltage-controlled limiter will operate in DC, AC and transient analysis modes.

The component tests the values of the upper and lower limit control inputs to make sure that they are spaced far enough apart to guarantee the existence of a linear range between them. The range is calculated as the difference between (upper limit control input (U) − VoUD − ULSR) and (lower limit control input (L) + VoLD + ULSR) and must be greater than or equal to zero.

The limiting levels may be individually set at fixed values or one or both limiting levels may be controlled by a variable voltage, depending on the desired application.

In the circuit shown below,  the upper voltage limit is set by adjusting the potentiometer supplying the Upper terminal on the VCL. The lower voltage limit is set by adjusting the potentiometer supplying the Lower terminal on the VCL. The potentiometers are adjusted by pressing U or SHIFT-U for the upper limit and L or SHIFT-L for the lower limit.

These settings may be adjusted to provide symmetrical or unsymmetrical clipping on the positive and negative peak excursions of the input waveform when these peaks exceed the set limit (clipping) values.


Current Limiter Block

This component models the behavior of an opamp or comparator at a high level of abstraction. All of its pins act as inputs; three of them also act as outputs. The component takes as input a voltage value from the "in" connector. It then applies the offset and gain, and derives from it an equivalent internal voltage, Veq, which it limits to fall between the positive and negative power supply inputs. If Veq is greater than the output voltage seen on the "out" connector, a sourcing current will flow from the output pin. Otherwise, if Veq is less than the output voltage, a sinking current will flow into the output pin.

Depending on the polarity of the current flow, either a sourcing or a sinking resistance (Rsrc or Rsnk) value is applied to govern the output voltage/output current relationship. The chosen resistance will continue to control the output current until it reaches a maximum value specified by either ISrcL or ISnkL. The latter mimics the current limiting behavior of many operational amplifier output stages.

During operation, the output current is reflected either in the positive or the negative power supply inputs, depending on the polarity of the output current. Thus, realistic power consumption as seen in the supply rails is modeled.

ULSR controls the voltage below positive input power and above negative input power beyond which Veq = k(input voltage + Off) is smoothed. ISrcSR specifies the current below ISrcL at which smoothing begins, and specifies the current increment above zero input current at which positive power begins to transition to zero. ISnkSR serves the same purpose with respect to ISnkL and negative power. VDSR specifies the incremental value above and below (Veq − output voltage) = 0 at which output resistance will be set to Rsrc and Rsnk, respectively. For values of (Veq − output voltage) less than VDSR and greater than −VDSR, output resistance is interpolated smoothly between Rsrc and Rsnk.

The current limiter block is also a representation of an operational amplifier with respect to the sourcing and sinking of current at the output and supply terminals.

If the current being sinked/sourced to the load is less than the rated maximum, as determined from rated maximum sink/source specifications for a particular opamp, operation of the opamp circuit will be as expected.

If the current to be sinked/sourced is greater than the rated maximum, as determined by a larger than normal input to the opamp circuit,  the current limiter will limit current to the specified safe maximum value, thus protecting the opamp and associated circuitry from damage.

In the example circuit shown below, the sink and source current limits are set to 2 mA and the circuit gain (K) is set to 1. For this case, output current should then be Iload = Vin*K/Rload.

The switch, activated by pressing S, applies either a positive or negative input to the 'op-amp' circuit. These input levels are such that the output current would be in excess of the rated value of 2.0mA. The current limit function limits the source or sink output to 2.0 mA.

If the input levels are reduced to 2V or less, then the output current will be as expected at Vin/Rload.

A sine wave input of 1.4v RMS or less will be passed undistorted through the "amplifier" while inputs greater than 1.4 v RMS will show limiting (clipping) at the peaks.


Voltage Hysteresis

This component is a simple buffer stage that provides hysteresis of the output with respect to the input. ViL and ViH specify the center voltage or current inputs about which the hysteresis effect operates. The output values are limited to VoL and VoH. The hysteresis value, H, is added to ViL and ViH in order to specify the points at which the slope of the hysteresis function would normally change abruptly as the input transitions from low to high values. The slope of the hysteresis function is smoothly varied whenever ISD is set greater than zero.

This component simulates a non-inverting comparator in which the comparison threshold is changed each time the input crosses the  threshold in effect at that instant. As the output changes state (high to low or low to high) , the threshold voltage is changed internally in such a manner that the input must continue to change until it reaches the new threshold.

In the example circuit shown below, the hysteresis value is set to 5V. This means that the two comparison thresholds at which the output changes are +5V and -5V.

As shown, the input triangle waveform rises from 0V and the output is at its lowest value (0V in this case), as the input crosses +5V (the upper threshold in comparator terms) the output changes to its highest value(+2V in this case). Internally in the hysteresis block the threshold is now changed to -5V, (the lower threshold).

The output continues to rise to a peak and then starts to decrease.

Note    The output changes only when the input crosses -5V. Internally, the threshold is changed again to the upper threshold and the process repeats.


Voltage Slew Rate

This component limits the absolute slope of the output, with respect to time, to some maximum or value. You can accurately model actual slew rate effects of over-driving an amplifier circuit by cascading the amplifier with this component. Maximum rising and falling slope values are expressed in volts per second.

The slew rate block will continue to raise or lower its output until the difference between input and output values is zero. After, it will resume following the input signal unless the slope again exceeds its rise or fall slope limits.

This component provides for introduction of selectable rising and falling slew rates (rise and fall times on a pulse waveform) for analysis of pulse and analog circuits.

With an ideal pulse or analog input to the block the effect of slew rate on a logic circuit or analog amplifier (discrete component or op-amp) output may be investigated.

In the example shown below, the function generator may be set for either square wave or sine wave output.

A slew rate of 8000V/sec for rising slope and 6000V/sec for falling slope shows as rise and fall time on an ideal 80Hz. square wave input. Signal degradation as a result of slew rate occurs when frequency is increased.

Switching the function generator to sine wave output 60 Hz. does not result in distortion. However, as frequency is increased, slew rate distortion on a sine wave will become evident at 200 Hz. and above. As frequency is increased, the sine wave deteriorates to a triangle shape.

A more serious degradation of output as a result of slew rate occurs when the input frequency is doubled to 200Hz.


Digital ICs Parts Bin

Electronics Workbench contains six different templates. These templates contain ICs that are widely used in the electronics industry. To see the ICs available from a particular series, click on the below list of templates.

For a list of abbreviations and acronyms used to describe the special characteristics of each chip, see the  Chip Abbreviation Table.

4XXX Template

74XX Template

741XX Template

742XX Template

743XX Template

744XX Template


7416 (Hex INVERTER (HC-OD))

This device contains six inverters. For correct performance, the open collector outputs require pull-up resistors. The higher voltage outputs make this device compatible with high-level MOS circuits. For this IC, we recommend the HC-OD model for realistic performance.

INVERTER gate truth table:

 A | Y

-------

 1 | 0

 0 | 1


7417 (Hex BUFFER (HC-OD))

This device contains six independent BUFFER/Drivers. For correct performance, the open collector outputs require pull-up resistors. The higher voltage outputs make this device compatible with high-level MOS circuits. For this IC, we recommend the HC-OD model for realistic performance.

BUFFER gate truth table:

 A | Y

-------

 0 | 0

 1 | 1


74XX Template

The 74XX component in the parts bin is a template. It has no pins or labels and cannot be wired into a circuit.

To use an IC (Integrated Circuit or chip), drag the template onto the circuit window. A list of available ICs for this family appears. Select the IC you want to include in your circuit. The correct graphic will appear containing labels and pins.

The 74XX template includes:

7400 (Quad 2-In NAND)

7402 (Quad 2-In NOR)

7403 (Quad 2-In NAND (LS-OC))

7404 (Hex INVERTER)

7405 (Hex INVERTER (LS-OC))

7406 (Hex INVERTER (HC-OD))

7407 (Hex BUFFER (HC-OD))

7408 (Quad 2-In AND)

7409 (Quad 2-In AND (LS-OC))

7410 (Tri 3-In NAND)

7411 (Tri 3-In AND)

7412 (Tri 3-In NAND (LS-OC))

7414 (Hex INVERTER (Schmitt))

7416 (Hex INVERTER (HC-OD))

7417 (Hex BUFFER (HC-OD))

7420 (Dual 4-In NAND)

7421 (Dual 4-In AND)

7422 (Dual 4-In NAND (LS-OC))

7425 (Dual 4-In NOR w/Strobe)

7426 (Quad 2-In NAND)

7427 (Tri 3-In NOR)

7428 (Quad 2-In NOR)

7430 (8-In NAND)

7432 (Quad 2-In OR)

7433 (Quad 2-In NOR (LS-OC))

7437 (Quad 2-In NAND)

7439 (Quad 2-In NAND (LS-OC))

7438 (Quad 2-In NAND (LS-OC))

7440 (Dual 4-In NAND)

7442 (4-BCD to 10-Decimal Dec)

7445 (BCD-to-Decimal Dec)

7447 (BCD-to-Seven-Segment Dec)

7451 (AND-OR-INVERTER)

7454 (4-wide AND-OR-INVERTER)

7455 (2-wide 4-In AND-OR-INVERTER)

7469 (Dual 4-bit Binary Counter)

7472 (AND-gated JK MS-SLV FF (pre, clr))

7473 (Dual JK FF (clr))

7474 (Dual D-type FF (pre, clr))

7475 (4-bit Bistable Latches)

7476 (Dual JK FF (pre, clr))

7477 (4-bit Bistable Latches)

7478 (Dual JK FF (pre,com clk&clr))

7486 (Quad 2-In XOR)

7490 (Decade Counter)

7491 (8-bit Shift Reg)

7492 (Divide-by-twelve Counter)

7493 (4-bit Binary Counter)


7400 (Quad 2-In NAND)

This device contains four independent 2-input NAND gates.

NAND gate truth table:

 A  B | Y

----------

 1  1 | 0

 0  X | 1

 X  0 | 1


7402 (Quad 2-In NOR)

This device contains four independent 2-input NOR gates.

NOR gate truth table:

 A  B | Y

----------

 1  X | 1

 X  1 | 1

 0  0 | 0


7403 (Quad 2-In NAND (LS-OC))

This device contains four independent 2-input NAND gates. For correct performance, the open collector outputs require pull-up resistors. For this IC, we recommend the LS-OC model for realistic performance.

NAND gate truth table:

 A | B | Y

---|---|---

 0 | 0 | 1

 0 | 1 | 1

 1 | 0 | 1

 1 | 1 | 0


7404 (Hex INVERTER)

This device contains six independent INVERTER gates.

INVERTER gate truth table:

 A | Y

-------

 1 | 0

 0 | 1


7405 (Hex INVERTER (LS-OC))

This device contains six independent INVERTER gates. For correct performance, the open collector outputs require pull-up resistors.

INVERTER gate truth table:

 A | Y

-------

 1 | 0

 0 | 1


7406 (Hex INVERTER (HC-OD))

This device contains six independent INVERTER gates. For correct performance, the open collector outputs require pull-up resistors. The higher voltage outputs make this device compatible with high-level MOS circuits. For this IC, we recommend the HC-OD model for realistic performance.

INVERTER gate truth table:

 A | Y

-------

 1 | 0

 0 | 1


7407 (Hex BUFFER (HC-OD))

This device contains six independent BUFFER/non-inverting gates. For correct performance, the open collector outputs require pull-up resistors. The higher voltage outputs make this device compatible with high-level MOS circuits. For this IC, we recommend the HC-OD model for realistic performance.

BUFFER gate truth table:

 A | Y

-------

 0 | 0

 1 | 1


7408 (Quad 2-In AND)

This device contains four independent 2-input AND gates.

AND gate truth table:

 A  B | Y

----------

 1  1 | 1

 0  X | 0

 X  0 | 0


7409 (Quad 2-In AND (LS-OC))

This device contains four independent 2-input AND gates. For correct performance, the open collector outputs require pull-up resistors. For this IC, we recommend the LS-OC model for realistic performance.

AND gate truth table:

 A  B | Y

----------

 1  1 | 1

 0  X | 0

 X  0 | 0


7410 (Tri 3-In NAND)

This device contains three independent 3-input NAND gates.

NAND gate truth table:

 A  B  C | Y

-------------

 1  1  1 | 0

 0  X  X | 1

 X  0  X | 1

 X  X  0 | 1


7411 (Tri 3-In AND)

This device contains three independent 3-input AND gates.

AND gate truth table:

 A  B  C | Y

-------------

 1  1  1 | 1

 0  X  X | 0

 X  0  X | 0

 X  X  0 | 0


7412 (Tri 3-In NAND (LS-OC))

This device contains three independent 3-input NAND gates. For correct performance, the open collector outputs require pull-up resistors. For this IC, we recommend the LS-OC model for realistic performance.

NAND gate truth table:

 A  B  C | Y

-------------

 1  1  1 | 0

 0  X  X | 1

 X  0  X | 1

 X  X  0 | 1


7414 (Hex INVERTER (Schmitt))

A key feature of this integrated circuit is its high noise immunity. Due the to the Schmitt-trigger action, this device is ideal for circuits that are susceptible to unwanted small signals, such as noise.

INVERTER gate truth table:

 A | Y

---|---

 0 | 1

 1 | 0

The voltage threshold levels are as follows:

VT- = 0.95V (at 5 Volt test condition).

VT+ = 1.8V (at 5 Volt test condition).


7420 (Dual 4-In NAND)

This device contains two independent 4-input NAND gates.

NAND gate truth table:

 A  B  C  D | Y

----------------

 1  1  1  1 | 0

 0  X  X  X | 1

 X  0  X  X | 1

 X  X  0  X | 1

 X  X  X  0 | 1


7421 (Dual 4-In AND)

This device contains two independent 4-input AND gates.

AND gate truth table:

 A  B  C  D | Y

----------------

 1  1  1  1 | 1

 0  X  X  X | 0

 X  0  X  X | 0

 X  X  0  X | 0

 X  X  X  0 | 0


7422 (Dual 4-In NAND (LS-OC))

This device contains two independent 4-input NAND gates. For correct performance, the open collector outputs require pull-up resistors. For this IC, we recommend the LS-OC model for realistic performance.

NAND gate truth table:

 A  B  C  D | Y

----------------

 1  1  1  1 | 0

 0  X  X  X | 1

 X  0  X  X | 1

 X  X  0  X | 1

 X  X  X  0 | 1


7425 (Dual 4-In NOR w/Strobe)

This device contains two independent 4-input NOR gates with strobe.

NOR gate with strobe truth table:

 A B C D G | Y

---------------

 1 X X X 1 | 0

 X 1 X X 1 | 0

 X X 1 X 1 | 0

 X X X 1 1 | 0

 0 0 0 0 X | 1

 X X X X 0 | 1


7426 (Quad 2-In NAND)
7426 (Quad 2-In NAND (HC-OD))

This device contains four independent 2-input NAND gates. The higher voltage outputs make this device compatible with high-level MOS circuits. For this IC, we recommend the HC-OD model for realistic performance.

NAND gate truth table:

 A  B  C  D | Y

----------------

 1  1  1  1 | 0

 0  X  X  X | 1

 X  0  X  X | 1

 X  X  0  X | 1

 X  X  X  0 | 1


7427 (Tri 3-In NOR)

This device contains three independent 3-input NOR gates.

NOR gate truth table:

 A  B  C | Y

-------------

 1  X  X | 0

 X  1  X | 0

 X  X  1 | 0

 0  0  0 | 1


7428 (Quad 2-In NOR)

This device contains four independent 2-input NOR gates.

NOR gate truth table:

 A  B | Y

----------

 1  X | 0

 X  1 | 0

 0  0 | 1


7430 (8-In NAND)

8-input NAND gate truth table:

 Inputs A through H   | Y

--------------------------

 All inputs 1         | 0

 One or more inputs 0 | 1


7432 (Quad 2-In OR)

This device contains four independent 2-input OR gates.

OR gate truth table:

 A  B | Y

----------

 1  X | 1

 X  1 | 1

 0  0 | 0


7433 (Quad 2-In NOR (LS-OC))

This device contains four independent 2-input NOR gates. For correct performance, the open collector outputs require pull-up resistors. For this IC, we recommend the LS-OC model for realistic performance.

NOR gate truth table:

 A  B | Y

----------

 1  X | 0

 X  1 | 0

 0  0 | 1


7437 (Quad 2-In NAND)

This device contains four independent 2-input NAND gates.

NAND gate truth table:

 A  B | Y

----------

 1  1 | 0

 0  X | 1

 X  0 | 1


7438 (Quad 2-In NAND (LS-OC))

This device contains four independent 2-input NAND gates. For correct performance, the open collector outputs require pull-up resistors. For this IC, we recommend the LS-OC model for realistic performance.

NAND gate truth table:

 A  B | Y

------|---

 1  1 | 0

 0  X | 1

 X  0 | 1


7440 (Dual 4-In NAND)

This device contains two independent 4-input NAND gate.

NAND gate truth table:

  Inputs   | Output

  A B C D  |   Y

-----------|---------

  1 1 1 1  |   0

  0 X X X  |   1

  X 0 X X  |   1

  X X 0 X  |   1

  X X X 0  |   1


7442 (4-BCD to 10-Decimal Dec)

4-line to 10-line decimal decoder:

    | BCD Inputs |   Decimal Outputs

 No.|  D C B A   | 0 1 2 3 4 5 6 7 8 9

----|------------|--------------------

  0 |  0 0 0 0   | 0 1 1 1 1 1 1 1 1 1

  1 |  0 0 0 1   | 1 0 1 1 1 1 1 1 1 1

  2 |  0 0 1 0   | 1 1 0 1 1 1 1 1 1 1

  3 |  0 0 1 1   | 1 1 1 0 1 1 1 1 1 1

  4 |  0 1 0 0   | 1 1 1 1 0 1 1 1 1 1

  --|------------|--------------------

  5 |  0 1 0 1   | 1 1 1 1 1 0 1 1 1 1

  6 |  0 1 1 0   | 1 1 1 1 1 1 0 1 1 1

  7 |  0 1 1 1   | 1 1 1 1 1 1 1 0 1 1

  8 |  1 0 0 0   | 1 1 1 1 1 1 1 1 0 1

  9 |  1 0 0 1   | 1 1 1 1 1 1 1 1 1 0

  --|------------|--------------------

  I |  1 0 1 0   | 1 1 1 1 1 1 1 1 1 1

  N |  1 0 1 1   | 1 1 1 1 1 1 1 1 1 1

  V |  1 1 0 0   | 1 1 1 1 1 1 1 1 1 1

  A |  1 1 0 1   | 1 1 1 1 1 1 1 1 1 1

  L |  1 1 1 0   | 1 1 1 1 1 1 1 1 1 1

  I |  1 1 1 1   | 1 1 1 1 1 1 1 1 1 1

  D |


7445 (BCD-to-Decimal Dec)

BCD-to-Decimal truth table:

       Inputs            Outputs

No. |  D C B A  |  0 1 2 3 4 5 6 7 8 9

----|-----------|---------------------

 0  |  0 0 0 0  |  0 1 1 1 1 1 1 1 1 1

 1  |  0 0 0 1  |  1 0 1 1 1 1 1 1 1 1

 2  |  0 0 1 0  |  1 1 0 1 1 1 1 1 1 1

 3  |  0 0 1 1  |  1 1 1 0 1 1 1 1 1 1

 4  |  0 1 0 0  |  1 1 1 1 0 1 1 1 1 1

----|-----------|---------------------

 5  |  0 1 0 1  |  1 1 1 1 1 0 1 1 1 1

 6  |  0 1 1 0  |  1 1 1 1 1 1 0 1 1 1

 7  |  0 1 1 1  |  1 1 1 1 1 1 1 0 1 1

 8  |  1 0 0 0  |  1 1 1 1 1 1 1 1 0 1

 9  |  1 0 0 1  |  1 1 1 1 1 1 1 1 1 0

----|-----------|---------------------

 I  |  1 0 1 0  |  1 1 1 1 1 1 1 1 1 1

 N  |  1 0 1 1  |  1 1 1 1 1 1 1 1 1 1

 V  |  1 1 0 0  |  1 1 1 1 1 1 1 1 1 1

 A  |  1 1 0 1  |  1 1 1 1 1 1 1 1 1 1

 L  |  1 1 1 0  |  1 1 1 1 1 1 1 1 1 1

 I  |  1 1 1 1  |  1 1 1 1 1 1 1 1 1 1

 D  |


7447 (BCD-to-Seven-Segment Dec)

The 7447 BCD(Binary-Coded Decimal)-to-seven-segment decoder translates a 4-bit BCD input into hexadecimal, and outputs high on the output pins corresponding to the hexadecimal representation of the BCD input. There are provisions for lamp testing and for blanking the outputs.

                   Inputs                Outputs

      __   ___               __ ___

No.   LT   RBI    D C B A    BI/RBO | a b c d e f g

----|----|-----|-----------|--------|--------------

 0  | 1  |  1  |  0 0 0 0  |   1    | 1 1 1 1 1 1 0

 1  | 1  |  X  |  0 0 0 1  |   1    | 0 1 1 0 0 0 0

 2  | 1  |  X  |  0 0 1 0  |   1    | 1 1 0 1 1 0 1

 3  | 1  |  X  |  0 0 1 1  |   1    | 1 1 1 1 0 0 1

----|----|-----|-----------|--------|--------------

 4  | 1  |  X  |  0 1 0 0  |   1    | 0 1 1 0 0 1 1

 5  | 1  |  X  |  0 1 0 1  |   1    | 1 0 1 1 0 1 1

 6  | 1  |  X  |  0 1 1 0  |   1    | 0 0 1 1 1 1 0

 7  | 1  |  X  |  0 1 1 1  |   1    | 1 1 1 0 0 0 0

----|----|-----|-----------|--------|--------------

 8  | 1  |  X  |  1 0 0 0  |   1    | 1 1 1 1 1 1 1

 9  | 1  |  X  |  1 0 0 1  |   1    | 1 1 1 0 0 1 1

10  | 1  |  X  |  1 0 1 0  |   1    | 0 0 0 1 1 0 1  <  I

11  | 1  |  X  |  1 0 1 1  |   1    | 0 0 1 1 0 0 1  <  N

----|----|-----|-----------|--------|--------------  <  V

12  | 1  |  X  |  1 1 0 0  |   1    | 0 1 0 0 0 1 1  <  A

13  | 1  |  X  |  1 1 0 1  |   1    | 1 0 0 1 0 1 1  <  L

14  | 1  |  X  |  1 1 1 0  |   1    | 0 0 0 1 1 1 1  <  I

15  | 1  |  X  |  1 1 1 1  |   1    | 0 0 0 0 0 0 0  <  D

----|----|-----|-----------|--------|--------------

BI  | X  |  X  |  X X X X  |   0    | 0 0 0 0 0 0 0

RBI | 1  |  0  |  0 0 0 0  |   0    | 0 0 0 0 0 0 0

LT  | 0  |  X  |  X X X X  |   1    | 1 1 1 1 1 1 1

__

BI  = active-low blanking input

____

RBI = active-low ripple-blanking input

___

LT  = active-low lamp-test input

Notes:

1.  The blanking input (BI) must be open or held at a high logic level when output functions 0 through 15 are desired. The ripple-blanking input (RBI) must be open or high if blanking of a decimal zero is not desired.

2.  When a low logic level is applied to the blanking input, all segment outputs are off regardless of any other input level.

3.  To place the device in lamp-test mode, RBO must be high when LT is low. This forces all lamps on.


7451 (AND-OR-INVERTER)

AND-OR INVERTER gate truth table:

 A  B  C  D | Y

----------------

 0  X  X  0 | 1

 X  0  0  X | 1

 0  X  0  X | 1

 X  0  X  0 | 1

 1  1  X  X | 0

 X  X  1  1 | 0


7454 (4-wide AND-OR-INVERTER)

4-wide AND-OR-INVERTER truth table:

    Inputs        | Output

A B C D E F G H   |   Y

------------------|-------

1 1 X X X X X X   |   0

X X 1 1 X X X X   |   0

X X X X 1 1 X X   |   0

X X X X X X 1 1   |   0

X X X X X X X X   |   1


7455 (2-wide 4-In AND-OR-INVERTER)

AND-OR-INVERTER truth table:

    Inputs        | Output

A B C D E F G H   |   Y

------------------|-------

1 1 1 1 1 1 1 1   |   0

1 1 1 1 X X X X   |   0

X X X X 1 1 1 1   |   0

X X X X X X X X   |   1


7469 (Dual 4-bit Binary Counter)

Counter number one has two sections - counter A(divide-by-2 section) and counter B, C, D (divide-by-8 section). Counter number two has only divide-by-sixteen section.

4-Bit Counter truth table:

 ___    ___

1CLR | 2CLR | 1QA 1QB 1QC 1QD | 2QA 2QB 2QC 2QD

-----|------|-----------------|----------------

  1  |   1  |     COUNT       |      COUNT

  1  |   0  |     COUNT       |  0   0   0   0

  0  |   1  |  0   0   0   0  |      COUNT

  0  |   0  |  0   0   0   0  |  0   0   0   0


7472 (AND-gated JK MS-SLV FF (pre, clr))

This device is equpped with an active-low pre and active-low clr. Therefore, the flip-flop begins accepting input from the JK input when the preset and clear are both high (hence AND-gated).

AND-gated JK Flip-flop truth table:

 ___   ___                      _

 PRE | CLR | CLK | J | K |   Q  Q

 ----|-----|-----|---|---|--------

  0  |  1  |  X  | X | X |   1  0

  1  |  0  |  X  | X | X |   0  1

  0  |  0  |  X  | X | X | UNSTABLE

  1  |  1  |  P  | 0 | 0 |  Q0 'Q0

  1  |  1  |  P  | 1 | 0 |   1  0

  1  |  1  |  P  | 0 | 1 |   0  1

  1  |  1  |  P  | 1 | 1 | Toggle

P = triggers on pulse (level sensitive)


7473 (Dual JK FF (clr))

This device contains 2-independent JK flip-flops.

JK flip-flop truth table:

 ___                _

 Clr Clk  J  K | Q  Q

---------------------

  0   X   X  X | 0  1

  1   P   0  0 | Hold

  1   P   1  0 | 1  0

  1   P   0  1 | 0  1

  1   P   1  1 | Toggle

P = triggers on pulse (level sensitive)


7474 (Dual D-type FF (pre, clr))

This device is equipped with active-low preset and active-low clear inputs.

D-type positive-edge-triggered flip-flop truth table:

 ___ ___            _

 PRE CLR Clk D | Q  Q

---------------------

  0   1   X  X | 1  0

  1   0   X  X | 0  1

  0   0   X  X | 1  1

  1   1  POS 1 | 1  0

  1   1  POS 0 | 0  1

  1   1   0  X | Hold

POS = positive-edge-triggered


7475 (4-bit Bistable Latches)

This device is ideal for use as temporary storage for binary information.

Bistable Latch truth table:

 Inputs|Outputs

       |     _

  D  C | Q   Q

-------|-------

  0  1 | 0   1

  1  1 | 1   0

  X  0 | Q0  Q0'


7476 (Dual JK FF (pre, clr))

JK flip-flop truth table:

 ___  ___                 _

 PRE  CLR  CLK  J  K | Q  Q

----------------------------

  0    1    X   X  X | 1  0

  1    0    X   X  X | 0  1

  0    0    X   X  X | 1  1

  1    1    P   0  0 | Hold

  1    1    P   1  0 | 1  0

  1    1    P   0  1 | 0  1

  1    1    P   1  1 | Toggle

P = pulse triggered (level sensitive)


7477 (4-bit Bistable Latches)

Bistable latch truth table:

 D C | L  H

-----------

 0 1 | 1  0

 1 1 | 1  0

 X 0 | Hold


7478 (Dual JK FF (pre, com clk & clr))

The 7478 contains two negative-edge triggered flip-flops with individual JK, individual preset, common clock and common clear inputs.

JK flip-flop truth table:

Preset | Clear |  J  K  | Clock |  Q  Q'

-----------------------------------------

  0    |   1   |  X  X  |   X   |  1  0

  1    |   0   |  X  X  |   X   |  0  1

  0    |   0   |  X  X  |   X   |  1* 1*  (unstable)

  1    |   1   |  0  0  |  NEG  |(no change)

  1    |   1   |  0  1  |  NEG  |  0  1

  1    |   1   |  1  0  |  NEG  |  1  0

  1    |   1   |  1  1  |  NEG  | (toggle)

  1    |   1   |  X  X  |   1   |(no change)

 * = This configuration will not persist when preset and clear are inactive.

NEG = transition from high to low


7486 (Quad 2-In XOR)

EXCLUSIVE-OR gate truth table:

 A  B | Y

----------

 0  0 | 0

 0  1 | 1

 1  0 | 1

 1  1 | 0


7490 (Decade Counter)

Decade Counter truth table:

          Reset in           |     Output

--------------------------------------------

 R0(1)  R0(2)  R9(1)  R9(2)  |  Qd Qc Qb Qa

--------------------------------------------

   1      1      0      X    |  0  0  0  0

   1      1      X      0    |  0  0  0  0

   X      X      1      1    |  1  0  0  1

   X      0      X      0    |    COUNT

   0      X      0      X    |    COUNT

   0      X      X      0    |    COUNT

   X      0      0      X    |    COUNT

The 7490 counts from 0 to 9 in binary.


7491 (8-bit Shift Reg)

Shift Register truth table:

            __

 A  B | Qh  Qh

---------------

 1  1 | 1   0

 0  X | 0   1

 X  0 | 0   1

_____ | Preset |   Preset   |     | Serial |        Outputs

Clear | Enable | A  B  C  D | Clk |        |  QA   QB   QC   QD   QE

------|--------|------------|-----|--------|------------------------

  0   |   0    | X  X  X  X |  X  |   X    |  0    0    0    0    0

  0   |   X    | 0  0  0  0 |  X  |   X    |  0    0    0    0    0

  1   |   1    | 1  1  1  1 |  X  |   X    |  1    1    1    1    1

  1   |   1    | 0  0  0  0 |  0  |   X    | QA0  QB0  QC0  QD0  QE0

  1   |   1    | 1  0  1  0 |  0  |   X    |  1   QB0   1   QD0   1

  1   |   0    | X  X  X  X |  0  |   X    | QA0  QB0  QC0  QD0  QE0

  1   |   0    | X  X  X  X | POS |   1    |  1   QAn  QBn  QCn  QDn

  1   |   0    | X  X  X  X | POS |   0    |  0   QAn  QBn  QCn  QDn

- POS = transition from low to high level

- QA0, QB0, etc. = the level of QA, QB, etc. respectively before the indicated steady state conditions were established

- QAn, QBn, etc. = the level of QA, QB, etc. respectively before the most recent negative transition of the clock


7492 (Divide-by-twelve Counter)

The 7492 counts from 0 to 11 in binary.

 Reset in  |  Output

--------------------------

 RO1  RO2  |  Qd Qc Qb Qa

--------------------------

  1    1   |  0  0  0  0

  0    X   |    Count

  X    0   |    Count


7493 (4-bit Binary Counter)

The 7493 counts from 0 to 15 in binary.

 Reset in  |  Output

--------------------------

 RO1  RO2  |  Qd Qc Qb Qa

--------------------------

  1    1   |  0  0  0  0

  0    X   |    Count

  X    0   |    Count


741XX Template

The 741XX component in the parts bin is a generic IC, or template. It has no pins or labels and cannot be wired into a circuit.

To use an IC, drag the template onto the circuit window. A list of available ICs for this family appears. Select the IC you want to include in your circuit. The correct graphic will appear containing labels and pins.

The 741XX template includes:

74107 (Dual JK FF(clr))

74109 (Dual JK' FF(+edge, pre, clr))

74112 (Dual JK FF(-edge, pre, clr))

74113 (Dual JK MS-SLV FF (-edge, pre))

74114 (Dual JK FF (-edge, pre, com clk & clr))

74116 (Dual 4-bit latches (clr))

74125 (Quad bus BUFFER w/3-state Out)

74126 (Quad bus BUFFER w/3-state Out)

74132 (Quad 2-In NAND (Schmitt))

74133 (13-In NAND)

74134 (12-In NAND w/3-state Out)

74138 (3-to-8 Dec)

74139 (Dual 2-to-4 Dec/DEMUX)

74145 (BCD-to-Decimal Dec)

74147 (10-to-4 Priority Enc)

74148 (8-to-3 Priority Enc)

74150 (1-of-16 Data Sel/MUX)

74151 (1-of-8 Data Sel/MUX)

74153 (Dual 4-to-1 Data Sel/MUX)

74154 (4-to-16 Dec/DEMUX)

74155 (Dual 2-to-4 Dec/DEMUX)

74156 (Dual 2-to-4 Dec/DEMUX (LS-OC))

74157 (Quad 2-to-1 Data Sel/MUX)

74158 (Quad 2-to-1 Data Sel/MUX)

74159 (4-to-16 Dec/DEMUX (LS-OC))

74160 (Sync 4-bit Decade Counter (clr))

74162 (Sync 4-bit Decade Counter)

74163 (Sync 4-bit Binary Counter)

74164 (8-bit Parallel-Out Serial Shift Reg)

74165 (Parallel-load 8-bit Shift Reg)

74166 (Parallel-load 8-bit Shift Reg)

74169 (Sync 4-bit up/down Binary Counter)

74173 (4-bit D-type Reg w/3-state Out)

74174 (Hex D-type FF (clr))

74175 (Quad D-type FF (clr))

74181 (Alu/Function Generator)

74190 (Sync BCD up/down Counter)

74191 (Sync 4-bit up/down Counter)

74192 (Sync BCD up/down Counter)

74194 (4-bit Bidirectional Univ. Shift Reg)

74195 (4-bit Parallel-Access Shift Reg)

74198 (8-bit Shift Reg (shl/shr ctrl))

74199 (8-bit Shift Reg (sh/ld ctrl))


74107 (Dual JK FF(clr))

JK flip-flop truth table:

___                 _

CLR  CLK  J  K | Q  Q

---------------|-----

 0    X   X  X | 0  1

 1    P   0  0 | Hold

 1    P   1  0 | 1  0

 1    P   0  1 | 0  1

 1    P   1  1 | Toggle


74109 (Dual JK FF (+edge, pre, clr))
74109 (Dual JK' FF (+edge, pre, clr))

JK flip-flop truth table:

___  ___                 _

PRE  CLR  CLK  J  K | Q  Q

--------------------|-----

 0    1    X   X  X | 1  0

 1    0    X   X  X | 0  1

 0    0    X   X  X | 1  1

 1    1   POS  0  0 | 0  1

 1    1   POS  1  0 | Toggle

 1    1   POS  0  1 | Hold

 1    1   POS  1  1 | 1  0

 1    1    0   X  X | Hold

POS = positive edge triggered


74112 (Dual JK FF(-edge, pre, clr))

JK flip-flop truth table:

___  ___                 _

PRE  CLR  CLK  J  K | Q  Q

--------------------|-----

 0    1    X   X  X | 1  0

 1    0    X   X  X | 0  1

 0    0    X   X  X | 1  1

 1    1   NEG  0  0 | 0  1

 1    1   NEG  1  0 | Toggle

 1    1   NEG  0  1 | Hold

 1    1   NEG  1  1 | 1  0

 1    1    0   X  X | Hold

NEG = negative edge triggered


74113 (Dual JK MS-SLV FF (-edge, pre))

JK flip-flop truth table:

___                 _

PRE  CLK  J  K | Q  Q

---------------|-----

 0    X   X  X | 1  0

 1   NEG  0  0 | Hold

 1   NEG  1  0 | 1  0

 1   NEG  0  1 | 0  1

 1   NEG  1  1 | Toggle

 1    1   X  X | Hold

NEG = negative edge triggered


74114 (Dual JK FF (-edge, pre, com clk & clr))

JK flip-flop truth table:

___ ___             _

PRE CLR CLK J K | Q Q

----------------|----

 0   0   X  X X | 1 0

 1   0   X  X X | 0 1

 0   0   X  X X | 1 1

 1   1  NEG 0 0 | Hold

 1   1  NEG 1 0 | 1 0

 1   1  NEG 0 1 | 0 1

 1   1  NEG 1 1 | Toggle

 1   1   1  X X | Hold

NEG = negative edge triggered


74116 (Dual 4-bit latches (clr))

4-Bit Latch truth table:

       INPUTS        | OUTPUT

___    ENABLE        |

CLR |  C1 C2  | DATA |   Q

----|---------|------|-------

 1  |  0  0   |   0  |   0

 1  |  0  0   |   1  |   1

 1  |  X  1   |   X  |  Hold

 1  |  1  X   |   X  |  Hold

 0  |  X  X   |   X  |   0


74125 (Quad bus BUFFER w/3-state Out)

This device contains four independent BUFFER/non-inverting gates with 3-state outputs.

BUFFER gate truth table:

     _

 A   G  |  Y

--------|----

 1   0  |  0

 0   0  |  1

 X   1  |  Z

The output of the bus buffer is disabled when G is high.


74126 (Quad bus BUFFER w/3-state Out)

This device contains four independent BUFFER/non-inverting gates with 3-state outputs.

BUFFER gate truth table:

 A   G  |  Y

--------|----

 1   1  |  1

 0   1  |  0

 X   0  |  Z

Z = high impedance (off)

The output of the bus buffer is disabled when G is low.


74132 (Quad 2-In NAND (Schmitt))

NAND gate truth table:

 A   B  |  Y

--------|----

 1   1  |  0

 0   X  |  1

 X   0  |  1

VT+ = 1.8V (at 5 Volt test condition).

VT- = 0.95V (at 5 Volt test condition).


74133 (13-In NAND)

NAND gate truth table:

Inputs A Thru M      |  Y

---------------------|---

All inputs 1         |  0

One or more inputs 0 |  1


74134 (12-In NAND w/3-state Out)

12-Input NAND with 3-state outputs:

                        __

Inputs A thru L      |  OC  |  Y

---------------------|------|----

All inputs 1         |  0   |  0

One or more inputs 0 |  0   |  1

Don't care           |  1   |  Z

Z = high impedance (off)


74138 (3-to-8 Dec)

3-to-8 decoder/demultiplexer truth table:

 __      __ | Select  |

 GL  G1  G2 | C  B  A | Y0  Y1  Y2  Y3  Y4  Y5  Y6  Y7

 -----------|---------|-------------------------------

 X   X   1  | X  X  X | 1   1   1   1   1   1   1   1

 X   0   X  | X  X  X | 1   1   1   1   1   1   1   1

 -----------|---------|-------------------------------

 0   1   0  | 0  0  0 | 0   1   1   1   1   1   1   1

 0   1   0  | 0  0  1 | 1   0   1   1   1   1   1   1

 0   1   0  | 0  1  0 | 1   1   0   1   1   1   1   1

 0   1   0  | 0  1  1 | 1   1   1   0   1   1   1   1

 -----------|---------|------------------------------

 0   1   0  | 1  0  0 | 1   1   1   1   0   1   1   1

 0   1   0  | 1  0  1 | 1   1   1   1   1   0   1   1

 0   1   0  | 1  1  0 | 1   1   1   1   1   1   0   1

 0   1   0  | 1  1  1 | 1   1   1   1   1   1   1   0

 -----------|---------|------------------------------

 1   1   0  | X  X  X | Output corresponding to stored

            |         | address 0; all others 1


74139 (Dual 2-to-4 Dec/DEMUX)

2-to-4 decoder/demultiplexer truth table:

       _    Select |    Outputs

Enable G     B   A | Y0  Y1  Y2  Y3

-------------------|---------------

    1        X   X | 1   1   1   1

    0        0   0 | 0   1   1   1

    0        0   1 | 1   0   1   1

    0        1   0 | 1   1   0   1

    0        1   1 | 1   1   1   0


74145 (BCD-to-Decimal Dec)

BCD to Decimal decoders/drivers truth table:

     |  INPUTS   |      OUTPUTS

 No. |  D C B A  | 0 1 2 3 4 5 6 7 8 9

 ----|-----------|---------------------

  O  |  0 0 0 0  | 0 1 1 1 1 1 1 1 1 1

  1  |  0 0 0 1  | 1 0 1 1 1 1 1 1 1 1

  2  |  0 0 1 0  | 1 1 0 1 1 1 1 1 1 1

  3  |  0 0 1 1  | 1 1 1 0 1 1 1 1 1 1

  4  |  0 1 0 0  | 1 1 1 1 0 1 1 1 1 1

 ----|-----------|---------------------

  5  |  0 1 0 1  | 1 1 1 1 1 0 1 1 1 1

  6  |  0 1 1 0  | 1 1 1 1 1 1 0 1 1 1

  7  |  0 1 1 1  | 1 1 1 1 1 1 1 0 1 1

  8  |  1 0 0 0  | 1 1 1 1 1 1 1 1 0 1

  9  |  1 0 0 1  | 1 1 1 1 1 1 1 1 1 0

  ---|-----------|---------------------

  I  |  1 0 1 0  | 1 1 1 1 1 1 1 1 1 1

  N  |  1 0 1 1  | 1 1 1 1 1 1 1 1 1 1

  V  |  1 1 0 0  | 1 1 1 1 1 1 1 1 1 1

  A  |  1 1 0 1  | 1 1 1 1 1 1 1 1 1 1

  L  |  1 1 1 0  | 1 1 1 1 1 1 1 1 1 1

  I  |  1 1 1 1  | 1 1 1 1 1 1 1 1 1 1

  D  |


74147 (10-to-4 Priority Enc)

10-Line to 4-Line Priority Encoder truth table:

     Inputs          Outputs

1 2 3 4 5 6 7 8 9 |  D C B A

------------------|-----------

1 1 1 1 1 1 1 1 1 |  1 1 1 1

X X X X X X X X 0 |  0 1 1 0

X X X X X X X 0 1 |  0 1 1 1

X X X X X X 0 1 1 |  1 0 0 0

X X X X X 0 1 1 1 |  1 0 0 1

X X X X 0 1 1 1 1 |  1 0 1 0

X X X 0 1 1 1 1 1 |  1 0 1 1

X X 0 1 1 1 1 1 1 |  1 1 0 0

X 0 1 1 1 1 1 1 1 |  1 1 0 1

0 1 1 1 1 1 1 1 1 |  1 1 1 0


74148 (8-to-3 Priority Enc)

8-Line to 3-Line Priority Encoder truth table:

        Inputs       |     Outputs

EI | 0 1 2 3 4 5 6 7 | A2 A1 A0 | GS EO

---|-----------------|----------|-------

 1 | X X X X X X X X |  1  1  1 |  1  1

 0 | 1 1 1 1 1 1 1 1 |  1  1  1 |  1  0

 0 | X X X X X X X 0 |  0  0  0 |  0  1

 0 | X X X X X X 0 1 |  0  0  1 |  0  1

 0 | X X X X X 0 1 1 |  0  1  0 |  0  1

 0 | X X X X 0 1 1 1 |  0  1  1 |  0  1

 0 | X X X 0 1 1 1 1 |  1  0  0 |  0  1

 0 | X X 0 1 1 1 1 1 |  1  0  1 |  0  1

 0 | X 0 1 1 1 1 1 1 |  1  1  0 |  0  1

 0 | 0 1 1 1 1 1 1 1 |  1  1  1 |  0  1


74151 (1-of-8 Data Sel/MUX)

Data selector/multiplexer truth table:

 Select  | Strobe | Outputs

C  B  A  |   G'   |  Y  W

---------|--------|--------

X  X  X  |   1    |  0  1

0  0  0  |   0    | D0  D0'

0  0  1  |   0    | D1  D1'

0  1  0  |   0    | D2  D2'

0  1  1  |   0    | D3  D3'

1  0  0  |   0    | D4  D4'

1  0  1  |   0    | D5  D5'

1  1  0  |   0    | D6  D6'

1  1  1  |   0    | D7  D7'


74153 (Dual 4-to-1 Data Sel/MUX)

Data selector/multiplexer truth table:

 Select |  Data Inputs   | Strobe | Output

  B  A  | C0  C1  C2  C3 |   G'   |   Y

 -------|----------------|--------|-------

  X  X  |  X   X   X   X |   1    |   0

  0  0  |  0   X   X   X |   0    |   0

  0  0  |  1   X   X   X |   0    |   1

  0  1  |  X   0   X   X |   0    |   0

  0  1  |  X   1   X   X |   0    |   1

  1  0  |  X   X   0   X |   0    |   0

  1  0  |  X   X   1   X |   0    |   1

  1  1  |  X   X   X   0 |   0    |   0

  1  1  |  X   X   X   1 |   0    |   1


74154 (4-to-16 Dec/DEMUX)

4-to-16 Decoder/Demultiplexer truth table:

_  _ Inputs     |             Outputs

G1 G2 | D C B A | 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

------|---------|--------------------------------------

0  0  | 0 0 0 0 | 0 1 1 1 1 1 1 1 1 1 1  1  1  1  1  1

0  0  | 0 0 0 1 | 1 0 1 1 1 1 1 1 1 1 1  1  1  1  1  1

0  0  | 0 0 1 0 | 1 1 0 1 1 1 1 1 1 1 1  1  1  1  1  1

0  0  | 0 0 1 1 | 1 1 1 0 1 1 1 1 1 1 1  1  1  1  1  1

0  0  | 0 1 0 0 | 1 1 1 1 0 1 1 1 1 1 1  1  1  1  1  1

0  0  | 0 1 0 1 | 1 1 1 1 1 0 1 1 1 1 1  1  1  1  1  1

0  0  | 0 1 1 0 | 1 1 1 1 1 1 0 1 1 1 1  1  1  1  1  1

0  0  | 0 1 1 1 | 1 1 1 1 1 1 1 0 1 1 1  1  1  1  1  1

0  0  | 1 0 0 0 | 1 1 1 1 1 1 1 1 0 1 1  1  1  1  1  1

0  0  | 1 0 0 1 | 1 1 1 1 1 1 1 1 1 0 1  1  1  1  1  1

0  0  | 1 0 1 0 | 1 1 1 1 1 1 1 1 1 1 0  1  1  1  1  1

0  0  | 1 0 1 1 | 1 1 1 1 1 1 1 1 1 1 1  0  1  1  1  1

0  0  | 1 1 0 0 | 1 1 1 1 1 1 1 1 1 1 1  1  0  1  1  1

0  0  | 1 1 0 1 | 1 1 1 1 1 1 1 1 1 1 1  1  1  0  1  1

0  0  | 1 1 1 0 | 1 1 1 1 1 1 1 1 1 1 1  1  1  1  0  1

0  0  | 1 1 1 1 | 1 1 1 1 1 1 1 1 1 1 1  1  1  1  1  0

0  1  | X X X X | 1 1 1 1 1 1 1 1 1 1 1  1  1  1  1  1

1  0  | X X X X | 1 1 1 1 1 1 1 1 1 1 1  1  1  1  1  1

1  1  | X X X X | 1 1 1 1 1 1 1 1 1 1 1  1  1  1  1  1


74155 (Dual 2-to-4 Dec/DEMUX)

Decoder/Demultiplexer truth table:

Select | Strobe | Data |      Outputs

 A  B  |   G'   |  C   | Y0  Y1  Y2  Y3

-------|--------|------|-----------------

 X  X  |   1    |  X   |  1   1   1   1

 0  0  |   0    |  1   |  0   1   1   1

 0  1  |   0    |  1   |  1   0   1   1

 1  0  |   0    |  1   |  1   1   0   1

 1  1  |   0    |  1   |  1   1   1   0

 X  X  |   X    |  0   |  1   1   1   1


74156 (Dual 2-to-4 Dec/DEMUX (LS-OC))

This device contains two 2-to-4 decoders/demultipexers. For this IC, we recommend the LS-OC model for realistic performance.

Decoder/Demultiplexer truth table:

Select | Strobe | Data |      Outputs

 A  B  |   G'   |  C   | Y0  Y1  Y2  Y3

-------|--------|------|----------------

 X  X  |   1    |  X   |  1   1   1   1

 0  0  |   0    |  1   |  0   1   1   1

 0  1  |   0    |  1   |  1   0   1   1

 1  0  |   0    |  1   |  1   1   0   1

 1  1  |   0    |  1   |  1   1   1   0

 X  X  |   X    |  0   |  1   1   1   1


74157 (Quad 2-to-1 Data Sel/MUX)

Data Selector/Multiplexer truth table:

Strobe | Select |      | Output

  G'   |  A'/B  | A  B |   Y

-------|--------|------|-------

  1    |   X    | X  X |   0

  0    |   0    | 0  X |   0

  0    |   0    | 1  X |   1

  0    |   1    | X  0 |   0

  0    |   1    | X  1 |   1


74158 (Quad 2-to-1 Data Sel/MUX)

Data Selector/Multiplexer truth table:

Strobe | Select |      | OUTPUT

  G'   |  A'/B  | A  B |   Y

-------|--------|------|-------

  1    |   X    | X  X |   1

  0    |   0    | 0  X |   1

  0    |   0    | 1  X |   0

  0    |   1    | X  0 |   1

  0    |   1    | X  1 |   0


74159 (4-to-16 Dec/DEMUX (LS-OC))

For this IC, we recommend the LS-OC model for realistic performance.

Decoder/Demultiplexer truth table:

_  _ Inputs     |             Outputs

G1 G2 | D C B A | 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

------|---------|--------------------------------------

0  0  | 0 0 0 0 | 0 1 1 1 1 1 1 1 1 1 1  1  1  1  1  1

0  0  | 0 0 0 1 | 1 0 1 1 1 1 1 1 1 1 1  1  1  1  1  1

0  0  | 0 0 1 0 | 1 1 0 1 1 1 1 1 1 1 1  1  1  1  1  1

0  0  | 0 0 1 1 | 1 1 1 0 1 1 1 1 1 1 1  1  1  1  1  1

0  0  | 0 1 0 0 | 1 1 1 1 0 1 1 1 1 1 1  1  1  1  1  1

0  0  | 0 1 0 1 | 1 1 1 1 1 0 1 1 1 1 1  1  1  1  1  1

0  0  | 0 1 1 0 | 1 1 1 1 1 1 0 1 1 1 1  1  1  1  1  1

0  0  | 0 1 1 1 | 1 1 1 1 1 1 1 0 1 1 1  1  1  1  1  1

0  0  | 1 0 0 0 | 1 1 1 1 1 1 1 1 0 1 1  1  1  1  1  1

0  0  | 1 0 0 1 | 1 1 1 1 1 1 1 1 1 0 1  1  1  1  1  1

0  0  | 1 0 1 0 | 1 1 1 1 1 1 1 1 1 1 0  1  1  1  1  1

0  0  | 1 0 1 1 | 1 1 1 1 1 1 1 1 1 1 1  0  1  1  1  1

0  0  | 1 1 0 0 | 1 1 1 1 1 1 1 1 1 1 1  1  0  1  1  1

0  0  | 1 1 0 1 | 1 1 1 1 1 1 1 1 1 1 1  1  1  0  1  1

0  0  | 1 1 1 0 | 1 1 1 1 1 1 1 1 1 1 1  1  1  1  0  1

0  0  | 1 1 1 1 | 1 1 1 1 1 1 1 1 1 1 1  1  1  1  1  0

0  1  | X X X X | 1 1 1 1 1 1 1 1 1 1 1  1  1  1  1  1

1  0  | X X X X | 1 1 1 1 1 1 1 1 1 1 1  1  1  1  1  1

1  1  | X X X X | 1 1 1 1 1 1 1 1 1 1 1  1  1  1  1  1


74160 (Sync 4-bit Decade Counter (clr))

Decade Counter truth table:

___   ____

CLR | LOAD | ENP | ENT | CLK | A B C D | QA  QB  QC  QD  RCO

----|------|-----|-----|-----|---------|--------------------

 0  |  X   |  X  |  X  |  X  | X X X X | 0   0   0   0    0

 1  |  0   |  0  |  0  | POS | X X X X | A   B   C   D    *1

 1  |  1   |  1  |  1  | POS | X X X X |       Count      *1

 1  |  1   |  1  |  X  |  X  | X X X X | QA0 QB0 QC0 QD0  *1

 1  |  1   |  X  |  1  |  X  | X X X X | QA0 QB0 QC0 QD0  *1

- *1 - RCO goes HIGH at count 9 to 0.


74162 (Sync 4-bit Decade Counter)

Decade Counter truth table:

___   ____

CLR | LOAD | ENP | ENT | CLK | A B C D | QA  QB  QC  QD  RCO

----|------|-----|-----|-----|---------|--------------------

 0  |  X   |  X  |  X  |  X  | X X X X | 0   0   0   0    0

 1  |  0   |  0  |  0  | POS | X X X X | A   B   C   D    *1

 1  |  1   |  1  |  1  | POS | X X X X |       Count      *1

 1  |  1   |  1  |  X  |  X  | X X X X | QA0 QB0 QC0 QD0  *1

 1  |  1   |  X  |  1  |  X  | X X X X | QA0 QB0 QC0 QD0  *1

- *1 - RCO goes HIGH at count 9 to 0.


74163 (Sync 4-bit Binary Counter)

4-Bit Counter truth table:

___   ____

CLR | LOAD | ENP | ENT | CLK | A B D C | QA  QB  QC  QD  RCO

----|------|-----|-----|-----|---------|--------------------

 0  |  X   |  X  |  X  |  X  | X X X X | 0   0   0   0    0

 1  |  0   |  0  |  0  | POS | X X X X | A   B   C   D    *1

 1  |  1   |  1  |  1  | POS | X X X X |       Count      *1

 1  |  1   |  1  |  X  |  X  | X X X X | QA0 QB0 QC0 QD0  *1

 1  |  1   |  X  |  1  |  X  | X X X X | QA0 QB0 QC0 QD0  *1

- *1 - RCO goes HIGH at count 15 to 0.


74164 (8-bit Parallel-Out Serial Shift Reg)

Shift Register truth table:

_____

Clear | Clk | A  B | QA   QB     QH

------|-----|------|---------------

  0   |  X  | X  X | 0    0      0

  1   |  0  | X  X | QA0  QB0    QH0

  1   | POS | 1  1 | 1    QAn    QGn

  1   | POS | 0  X | 0    QAn    QGn

  1   | POS | X  0 | 0    QAn    QGn

- POS = positive-edge triggered

- QA0, QB0, QH0 = the level of QA, QB, QH respectively before the indicated steady state input conditions were established

- QAn, QGn = the level of QA or QG before the most recent positive transition of the clock; indicates one-bit shift


74165 (Parallel-load 8-bit Shift Reg)

This serial Shift-Register shifts the data in the direction of QA toward QH when clocked. To load the data at the 8-inputs into the device, apply a low level at the shift/load input. This register is equipped with a complementary output at the eighth bit.

                      INPUTS                   INTERNAL  |

 SHIFT/ |                          PARALLEL  | __O/P __  |OUTPUTS

 LOAD   |CLK INH | CLK | SERIAL | A  B  C  D | QA    QB  |  QH

--------|--------|-----|--------|------------|-----------|----

   0    |    X   |  X  |    X   | a  b  c  d |  a     b  |   h

   1    |    0   |  0  |    X   | X  X  X  X | QA0   QB0 |  QH0

   1    |    0   | POS |    1   | X  X  X  X |  1    QAn |  QGn

   1    |    0   | POS |    0   | X  X  X  X |  0    QAn |  QGn

   1    |    1   |  X  |    X   | X  X  X  X | QA0   QB0 |  QH0

POS = transition from low to high

a, b, c, d = the level of steady state input at A, B, C, or D respectively


74169 (Sync 4-bit up/down Binary Counter)

Up/down counter truth table:

___ ___     _         ____                             ___

ENP ENT | D/U | CLK | LOAD | A B C D | QA  QB  QC  QD  RCO

--------|-----|-----|------|---------|--------------------

 0 | 0  |  X  |  X  |  0   | X X X X | A   B   C   D    1*

 0 | 0  |  1  | POS |  1   | X X X X |   Count Down     1*

 0 | 0  |  0  | POS |  1   | X X X X |   Count Up       1*

 1 | X  |  X  |  X  |  X   | X X X X | Qa0 Qb0 Qc0 Qd0  1*

 X | 1  |  X  |  X  |  X   | X X X X | Qa0 Qb0 Qc0 Qd0  1*

- 1* = during the UP count RCO goes LOW at count 15,

--- during the DOWN count RCO goes LOW at count 0.


74173 (4-bit D-type Reg w/3-state Out)

D-type Register Truth table:

            | DATA ENABLE | DATA | OUTPUT

CLEAR | CLK | G'1    G'2  |  D   |   Q

------|-----|-------------|------|-------

  1   |  X  |  X      X   |  X   |   0

  0   |  0  |  X      X   |  X   |   Q0

  0   | POS |  1      X   |  X   |   Q0

  0   | POS |  X      1   |  X   |   Q0

  0   | POS |  0      0   |  0   |   0

  0   | POS |  0      0   |  1   |   1


74174 (Hex D-type FF (clr))

D-type flip-flop truth table:

                        _

CLEAR | CLK | D | Q    Q

------|-----|---|--------

  0   |  X  | X | 0    1

  1   | POS | 1 | 1    0

  1   | POS | 0 | 0    1

  1   |  0  | X | Q0  QO'


74175 (Quad D-type FF (clr))

D flip-flop truth table:

                       _

CLEAR | CLK | D | Q    Q

------|-----|---|--------

  0   |  X  | X | 0    1

  1   | POS | 1 | 1    0

  1   | POS | 0 | 0    1

  1   |  0  | X | Q0  QO'


74181 (Alu/Function Generator)

ALU/Function Generator truth table:

                     Active-low Data

                  M=H     |    M=L; Arithmetic Operations

 Selection  |    LOGIC    |     Cn=L            |    Cn=H

S3 S2 S1 S0 |  FUNCTIONS  |  (no carry)         |(with carry)

------------|-------------|---------------------|-------------

            |    _        |                     |

0  0  0  0  | F= A        | F=A MINUS 1         | F=A

            |    __       |                     |

0  0  0  1  | F= AB       | F= AB MINUS 1       | F=AB

            |    _        |     _               |    _

0  0  1  0  | F= A+B      | F= AB MINUS 1       | F=AB

            |             |                     |

0  0  1  1  | F= 1        | F=MINUS 1(2's comp) | F=Zero

            |    ___      |             _       |            _

0  1  0  0  | F= A+B      | F=A PLUS (A+B)      | F=A PLUS(A+B) Plus 1

            |    _        |             _       |             _

0  1  0  1  | F= B        | F=AB PLUS(A+B)      | F=AB PLUS(A+B)Plus 1

            |    _______  |                     |

0  1  1  0  | F= A "+" B  | F=A MINUS B MINUS 1 | F= A MINUS B

            |      _      |      _              |       _

0  1  1  1  | F= A+B      | F= A+B              | F= (A+B) PLUS 1

            |    _        |                     |

1  0  0  0  | F= AB       | F= A PLUS (A+B)     | F=A PLUS(A+B)PLUS 1

            |             |                     |

1  0  0  1  | F= A "+" B  | F= A PLUS B         | F=A PLUS B PLUS 1

            |             |     _               |

1  0  1  0  | F = B       | F= AB PLUS (A+B)    | F=AB PLUS (A+B)PLUS 1

            |             |                     |

1  0  1  1  | F = A + B   | F = (A + B)         | F=(A+B)PLUS 1

            |             |                     |

1  1  0  0  | F = 0       | F = A PLUS A        | F=A PLUS A PLUS 1

            |      _      |                     |

1  1  0  1  | F = AB      | F= AB PLUS A        | F=AB PLUS A PLUS 1

            |             |    _                |    _

1  1  1  0  | F=AB        | F=AB PLUS A         | F=AB PLUS A PLUS 1

            |             |                     |

1  1  1  1  | F = A       | F = A               | F= A PLUS 1


74190 (Sync BCD up/down Counter)

Up/Down Counter truth table:

____     _         ____                                    ___

CTEN | D/U | CLK | LOAD | A B C D | QA  QB  QC  QD MAX/MIN RCO

-----|-----|-----|------|---------|---------------------------

  0  |  X  |  X  |  0   | X X X X | A   B   C   D    1*     2*

  0  |  1  | POS |  1   | X X X X |   Count Down     1*     2*

  0  |  0  | POS |  1   | X X X X |   Count Up       1*     2*

  1  |  X  |  X  |  X   | X X X X | Qa0 Qb0 Qc0 Qd0  1*     2*

- 1* = during the UP count MAX/MIN goes HIGH at count 9, during the DOWN count MAX/MIN goes HIGH at count 0.

                                                  ____                                                                                            ____

- 2* = during the UP count RCO goes LOW at count 9, during the DOWN count RCO goes LOW at count 0.


74191 (Sync 4-bit up/down Counter)

Up/Down Counter truth table:

____     _         ____                                    ___

CTEN | D/U | CLK | LOAD | A B C D | QA  QB  QC  QD MAX/MIN RCO

-----|-----|-----|------|---------|---------------------------

  0  |  X  |  X  |  0   | X X X X | A   B   C   D    1*     2*

  0  |  1  | POS |  1   | X X X X |   Count Down     1*     2*

  0  |  0  | POS |  1   | X X X X |   Count Up       1*     2*

  1  |  X  |  X  |  X   | X X X X | Qa0 Qb0 Qc0 Qd0  1*     2*

- 1* = during the UP count MAX/MIN goes HIGH at count 15, during the DOWN count MAX/MIN goes HIGH at count 0.

                                                  ____                                                                                              ____

- 2* = during the UP count RCO goes LOW at count 15, during the DOWN count RCO goes LOW at count 0.


74192 (Sync BCD up/down Counter)

Up/Down Counter truth table:

                   ____ |  PARALLEL  |  OUTPUTS     __ __

CLEAR | UP DOWN  | LOAD | A  B  C  D |  QA QB QC QD CO BO

------|----------|------|------------|---------------------

  1   |  X    X  |  X   | X  X  X  X |  0  0  0  0  1  1

  0   |  X    X  |  0   | X  X  X  X |  A  B  C  D  1  1

  0   | POS   1  |  1   | X  X  X  X |  Count UP    *  *

  0   |  1   POS |  1   | X  X  X  X |  Count Down  *  *

- POS = transition from low to high

- a, b, c, d = the level of steady state input at inputs A, B, C, or D respectively

- * = during the UP count CO goes low from count 9 to 0, BO goes low from count 0 to 9 while counting DOWN


74194 (4-bit Bidirectional Univ. Shift Reg)

Shift Register truth table:

_____ |  MODE  |     |   SERIAL    |  PARALLEL  | OUTPUTS

CLEAR | S1  S0 | CLK | LEFT  RIGHT | A  B  C  D | QA   QB   QC   QD

------|--------|-----|-------------|------------|------------------

  0   | X   X  |  X  |  X      X   | X  X  X  X |  0    0    0    0

  1   | X   X  |  0  |  X      X   | X  X  X  X | QA0  QB0  QC0  QD0

  1   | 1   1  | POS |  X      X   | a  b  c  d |  a    b    c    d

  1   | 0   1  | POS |  X      1   | X  X  X  X |  1   QAn  QBn  QCn

  1   | 0   1  | POS |  X      0   | X  X  X  X |  0   QAn  QBn  QCn

  1   | 1   0  | POS |  1      X   | X  X  X  X | QBn  QCn  QDn   1

  1   | 1   0  | POS |  0      X   | X  X  X  X | QBn  QCn  QDn   0

  1   | 0   0  |  X  |  X      X   | X  X  X  X | QA0  QB0  QC0  QD0

- POS = transition from low to high

- a, b, c, d = the level of steady state input at inputs A, B, C, or D respectively

- QA0, QB0, QC0, QD0 = the level of QA, QB, QC, or QD, respectively, before the indicated steady state input conditions were established

- QAn, QBn, QCn, QDn = the level of QA, QB, QC, or QD before the most recent negative transition  of the clock.


74195 (4-bit Parallel-Access Shift Reg)

Shift Register truth table:

      | SHIFT/ |     | SERIAL |  PARALLEL  |       OUTPUTS

CLEAR | LOAD'  | CLK | J   K' | A  B  C  D | QA    QB   QC   QD   Q'D

------|--------|-----|--------|------------|--------------------------

  0   |   X    |  X  | X   X  | X  X  X  X |  0     0    0    0    1

  1   |   0    | POS | X   X  | a  b  c  d |  a     b    c    d    d'

  1   |   1    |  0  | X   X  | X  X  X  X | QA0   QB0  QC0  QD0  Q'D0

  1   |   1    | POS | 0   1  | X  X  X  X | QA0   QA0  QBn  QCn  Q'Cn

  1   |   1    | POS | 0   0  | X  X  X  X |  0    QAn  QBn  QCn  Q'Cn

  1   |   1    | POS | 1   1  | X  X  X  X |  1    QAn  QBn  QCn  Q'Cn

  1   |   1    | POS | 1   0  | X  X  X  X | Q'An  QAn  QBn  QCn  Q'Cn

- POS = transition from low to high

- a, b, c, d = the level of steady state input at A, B, C, or D respectively

- QA0, QB0, QC0, QD0 = the level of QA, QB, QC, QD respectively before the indicated steady state input conditions were established

- QAn, QBn, QCn = the level of QA, QB, QC respectively, before the most recent transition of the clock


74198 (8-bit Shift Reg (shl/shr ctrl))

Shift Register truth table:

_____ |  MODE  |     |   SERIAL    | PARALLEL |      OUTPUTS

CLEAR | S1  S0 | CLK | LEFT  RIGHT | A ... h  | QA   QB ... QG   QH

------|--------|-----|-------------|----------|--------------------

  0   | X    X |  X  |  X      X   |    X     |  0    0      0    0

  1   | X    X |  0  |  X      X   |    X     | QA0  QB0    QG0  QH0

  1   | 1    1 | POS |  X      X   | a ... h  |  a    b      g    h

  1   | 0    1 | POS |  X      1   |    X     |  1   QAn    QFn  QGn

  1   | 0    1 | POS |  X      0   |    X     |  0   QAn    QFn  QGn

  1   | 1    0 | POS |  1      X   |    X     | QBn  QCn    QHn   1

  1   | 1    0 | POS |  0      X   |    X     | QBn  QCn    QHn   1

  1   | 0    0 |  X  |  X      X   |    X     | QA0  QB0    QG0  QH0

- POS = transition from low level to high level

- a...h = the level of steady state input at inputs A through H respectively

- QA0, QB0, QG0, QH0 = the level of QA, QB, QG or QH, respectively, before the indicated steady state input conditions were established

- QAn, QBn etc. = the level of QA, QB, etc., respectively, before the most recent negative transition of the clock


74199 (8-bit Shift Reg (sh/ld ctrl))

This device contains an 8-bit Shift Register with shift/load control.

Shift Register truth table:

       Mode                | SERIAL |

_____ |   _ |        |     |     _  | PARALLEL|      OUTPUTS

CLEAR | S/L | CLKINH | CLK |  J  K  |  A...H  | QA  QB..QG  QH

------|-----|--------|-----|--------|---------|---------------

  0   |  X  |   X    |  X  |  X  X  |    X    |  0   0  0   0

  1   |  X  |   0    |  0  |  X  X  |    X    | QA0 QB0 QG0 QH0

  1   |  0  |   0    | POS |  X  X  |  a...h  |  a   b..g   h

  1   |  1  |   0    | POS |  0  1  |    X    | QA0 QA0 QBn QGn

  1   |  1  |   0    | POS |  0  0  |    X    |  0  QAn QFn QGn

  1   |  1  |   0    | POS |  1  1  |    X    |  1  QCn QHn  1

  1   |  1  |   0    | POS |  1  0  |    X    | 'QAn QAn QBn QGn

  1   |  X  |   1    | POS |  X  X  |    X    | QA0 QB0 QG0 QH0

- POS = transition from low level to high level

- a...h = the level of steady state input at inputs A through H respectively

- QA0, QB0, QG0, QH0 = the level of QA, QB, QG or QH, respectively, before the indicated steady state input conditions were established

- QAn, QBn etc. = the level of QA, QB, etc., respectively, before the most recent negative transition of the clock


742XX Template

The 742XX component in the parts bin is a generic IC, or template. It has no pins or labels and cannot be wired into a circuit.

To use an IC, drag the template onto the circuit window. A list of available ICs for this family appears. Select the IC you want to include in your circuit. The correct graphic will appear containing labels and pins.

The 742XX template includes:

74238 (3-to-8 line Dec/DEMUX)

74240 (Octal BUFFER w/3-state Out)

74241 (Octal BUFFER w/3-state Out)

74244 (Octal BUFFER w/3-state Out)

74251 (Data Sel/MUX w/3-state Out)

74253 (Dual 4-to-1 Data Sel/MUX w/3-state Out)

74257 (Quad 2-to-1 line Data Sel/MUX)

74258 (Quad 2-to-1 line Data Sel/MUX)

74266 (Quad 2-In XNOR (LS-OC))

74273 (Octal D-type FF)

74279 (Quad SR latches)

74280 (9-bit odd/even parity generator/checker)

74290 (Decade Counter)

74293 (4-bit Binary Counter))

74298 (Quad 2-In MUX)


74238 (3-to-8 line Dec/DEMUX)

The logic levels at the C B and A inputs select one of the eight lines. G1 is an active-high enable input while G2A and G2B are active-low enable inputs.

3-to-8 decoder/demultiplexer truth table:

   _   _   | Select  |           OUTPUTS

G1 G2A G2B | C  B  A | Y0  Y1  Y2  Y3  Y4  Y5  Y6  Y7

-----------|---------|-------------------------------

X   1   X  | X  X  X | 0   0   0   0   0   0   0   0

X   X   1  | X  X  X | 0   0   0   0   0   0   0   0

0   X   X  | X  X  X | 0   0   0   0   0   0   0   0

-----------|---------|-------------------------------

1   0   0  | 0  0  0 | 1   0   0   0   0   0   0   0

1   0   0  | 0  0  1 | 0   1   0   0   0   0   0   0

1   0   0  | 0  1  0 | 0   0   1   0   0   0   0   0

1   0   0  | 0  1  1 | 0   0   0   1   0   0   0   0

-----------|---------|-------------------------------

1   0   0  | 1  0  0 | 0   0   0   0   1   0   0   0

1   0   0  | 1  0  1 | 0   0   0   0   0   1   0   0

1   0   0  | 1  1  0 | 0   0   0   0   0   0   1   0

1   0   0  | 1  1  1 | 0   0   0   0   0   0   0   1


74240 (Octal BUFFER w/3-state Out)

Octal BUFFER gate truth table:

      Inputs         Outputs

 _               |

 G | A1 A2 A3 A4 | Y1 Y2 Y3 Y4

---|-------------|-------------

 1 | X  X  X  X  | Z  Z  Z  Z

   |             | __ __ __ __

 0 | X  X  X  X  | A1 A2 A3 A4

- Z = High impedance (off)


74241 (Octal BUFFER w/3-state Out)

Octal BUFFER gate truth table:

 _     Inputs       Outputs

 G | A1 A2 A3 A4 | Y1 Y2 Y3 Y4

---|-------------|------------

 1 | X  X  X  X  | Z  Z  Z  Z

 0 | X  X  X  X  | A1 A2 A3 A4

- Z = High impedance (off)

- A1, A2... = The level of the respective input


74244 (Octal BUFFER w/3-state Out)

Octal BUFFER gate truth table:

 _     Inputs       Outputs

 G | A1 A2 A3 A4 | Y1 Y2 Y3 Y4

---|-------------|------------

 1 | X  X  X  X  | Z  Z  Z  Z

 0 | X  X  X  X  | A1 A2 A3 A4

- Z = High impedance (off)

- A1, A2... = The level of the respective input


74251 (Data Sel/MUX w/3-state Out)

Data selector/multiplexer truth table:

C   B   A |  G  |  Y    W

----------|-----|---------

X   X   X |  1  |  Z    Z

0   0   0 |  0  |  D0   D0'

0   0   1 |  0  |  D1   D1'

0   1   0 |  0  |  D2   D2'

0   1   1 |  0  |  D3   D3'

1   0   0 |  0  |  D4   D4'

1   0   1 |  0  |  D5   D5'

1   1   0 |  0  |  D6   D6'

1   1   1 |  0  |  D7   D7'

- Z = high impedance (off)

- D0, D1...D7 = the level of the respective D input


74253 (Dual 4-to-1 Data Sel/MUX w/3-state Out)

Data selector/multiplexer truth table:

                          _

XB   A | C0  C1  C2  C3 | G | Y

-------|----------------|---|---

X    X | X   X   X   X  | 1 | Z

0    0 | 0   X   X   X  | 0 | 0

0    0 | 1   X   X   X  | 0 | 1

0    1 | X   0   X   X  | 0 | 0

0    1 | X   1   X   X  | 0 | 1

1    0 | X   X   0   X  | 0 | 0

1    0 | X   X   1   X  | 0 | 1

1    1 | X   X   X   0  | 0 | 0

1    1 | X   X   X   1  | 0 | 1

Z = high impedance (off)


74257 (Quad 2-to-1 line Data Sel/MUX)

Data selector/multiplexer truth table:

OUTPUT  |

CONTROL | SELECT | A  B | Y

--------|--------|------|---

   1    |   X    | X  X | Z

   0    |   0    | 0  X | 0

   0    |   0    | 1  X | 1

   0    |   1    | X  0 | 0

   0    |   1    | X  1 | 1

Z = high impedance (off)


74258 (Quad 2-to-1 line Data Sel/MUX)

Data selector/multiplexer truth table:

OUTPUT  |

CONTROL | SELECT | A  B | Y

--------|--------|------|---

   1    |   X    | X  X | Z

   0    |   0    | 0  X | 0

   0    |   0    | 1  X | 1

   0    |   1    | X  0 | 0

   0    |   1    | X  1 | 1

Z = high impedance (off)


74266 (Quad 2-In XNOR (LS-OC))

This device contains four independent 2-input EXCLUSIVE-NOR gates. For this IC, we recommend the LS-OC model for realistic performance.

Exclusive-NOR gate truth table:

 A  B | Y

----------

 0  0 | 1

 0  1 | 0

 1  0 | 0

 1  1 | 1


74273 (Octal D-type FF)

D flip-flop truth table:

CLEAR  CLK  D | Q

--------------|---

  0     X   X | 0

  1    POS  1 | 1

  1    POS  0 | 0

  1     0   X | Q0

POS = transition from low to high


74279 (Quad SR latches)

The RS flip-flop has an undesired operating condition, where 1 levels at both inputs will cause both outputs to go to a 0 level. This undefined condition must be avoided. Circuits involving feedback will lead to a "race condition" where the output will be unpredictable.

RS flip-flop truth table:

S   R  |  Q  Q'

-------|-------

0   0  |  -  -  (no change)

0   1  |  0  1

1   0  |  1  0

1   1  |  x  x  (undefined)


74280 (9-bit odd/even parity generator/checker)

9-bit odd/even parity generator/checker truth table:

NUMBER of inputs          |

A through I that are high | S-EVEN  S-ODD

--------------------------|--------------

   0, 2, 4, 6, 8          |    1      0

   1, 3, 5, 7, 9          |    0      1

S = sigma


74290 (Decade Counter)

Decade Counter truth table:

 COUNT | QD  QC  QB  QA      R0(1) R0(2) R9(1) R9(2) | QD  QC  QB  QA

 ------|---------------      ------------------------|---------------

   0   | 0   0   0   0        1     1     0     X    | 0   0   0   0

   1   | 0   0   0   1        1     1     X     0    | 0   0   0   0

   2   | 0   0   1   0        X     X     1     1    | 1   0   0   1

   3   | 0   0   1   1        X     0     X     0    |    COUNT

   4   | 0   1   0   0        0     X     0     X    |    COUNT

   5   | 0   1   0   1        0     X     X     0    |    COUNT

   6   | 0   1   1   0        X     0     0     X    |    COUNT

   7   | 0   1   1   1

   8   | 1   0   0   0

   9   | 1   0   0   1


74293 (4-bit Binary Counter)

The 74293 counts from 0 to 15 in binary.

Counter truth table:

 RESET IN     OUTPUT

 ___  ___

 Ro1  Ro2  |  Qd Qc Qb Qa

--------------------------

  1    1   |  0  0  0  0

  0    X   |    COUNT

  X    0   |    COUNT


74298 (Quad 2-In MUX)

Multiplexer truth table:

WORD

SELECT  CLK | QA   QB   QC   QD

------------|------------------

  0     NEG | a1   b1   c1   d1

  1     NEG | a2   b2   c2   d2

  X      1  | QA0  QB0  QC0  QD0

- NEG = transition from high to low

- a1, a2 etc. = the level of steady state input at A1, A2, etc.

- QA0, QB0, etc. = the level of QA, QB, etc. entered on the most recent negative transition of the clock input


743XX Template

The 743XX component in the parts bin is a generic IC, or template. It has no pins or labels and cannot be wired into a circuit.

To use an IC, drag the template onto the circuit window. A list of available ICs for this family appears. Select the IC you want to include in your circuit. The correct graphic will appear containing labels and pins.

The 743XX template includes:

74350 (4-bit Shifter w/3-state Out)

74352 (Dual 4-to-1 Data Sel/MUX)

74353 (Dual 4-to-1 Data Sel/MUX w/3-state Out)

74365 (Hex Bus Driver w/3-state Out)

74367 (Hex Bus Driver w/3-state Out)

74368 (Hex Bus Driver w/3-state Out)

74373 (Octal D-type Transparent Latches)

74374 (Octal D-type FF (+edge))

74375 (4-bit Bistable Latches)

74377 (Octal D-type FF w/en)

74378 (Hex D-type FF w/en)

74379 (Quad D-type FF w/en)

74393 (Dual 4-bit Binary Counter)

74395 (4-bit Cascadable Shift Reg w/3-state Out)


74350 (4-bit Shifter w/3-state Out)

4-Bit Shifter truth table:

__ Inputs      Outputs

OE  S1  S0  | Y0  Y1  Y2  Y3

------------|----------------

 1   X   X  |  Z   Z   Z   Z

 0   0   0  | D0  D1  D2  D3

 0   0   1  | D-1 D0  D1  D2

 0   1   0  | D-2 D-1 D0  D1

 0   1   1  | D-3 D-2 D-1 D0

- Z = High impedance (off)


74352 (Dual 4-to-1 Data Sel/MUX)

Data selector/multiplexer truth table:

SELECT |  DATA INPUTS    | _ |

 B   A | C0  C1  C2  C3  | G | Y

-------|-----------------|---|---

 X   X |  X   X   X   X  | 1 | 1

 0   0 |  0   X   X   X  | 0 | 1

 0   0 |  1   X   X   X  | 0 | 0

 0   1 |  X   0   X   X  | 0 | 1

 0   1 |  X   1   X   X  | 0 | 0

 1   0 |  X   X   0   X  | 0 | 1

 1   0 |  X   X   1   X  | 0 | 0

 1   1 |  X   X   X   0  | 0 | 1

 1   1 |  X   X   X   1  | 0 | 0


74353 (Dual 4-to-1 Data Sel/MUX w/3-state Out)

Data selector/multiplexer truth table:

SELECT |  DATA INPUTS    | _ |

 B   A | C0  C1  C2  C3  | G | Y

-------|-----------------|---|---

 X   X |  X   X   X   X  | 1 | 1

 0   0 |  0   X   X   X  | 0 | 1

 0   0 |  1   X   X   X  | 0 | 0

 0   1 |  X   0   X   X  | 0 | 1

 0   1 |  X   1   X   X  | 0 | 0

 1   0 |  X   X   0   X  | 0 | 1

 1   0 |  X   X   1   X  | 0 | 0

 1   1 |  X   X   X   0  | 0 | 1

 1   1 |  X   X   X   1  | 0 | 0


74365 (Hex Bus Driver w/3-state Out)

Hex Bus Driver truth table:

__  __       Inputs             |

G1  G2 | A1  A2  A3  A4  A5  A6 |  Y1  Y2  Y3  Y4  Y5  Y6

-------|------------------------|------------------------

0   0  | X   X   X   X   X   X  |  A1  A2  A3  A4  A5  A6

X   X  | X   X   X   X   X   X  |  Z   Z   Z   Z   Z   Z


74367 (Hex Bus Driver w/3-state Out)

Hex Bus Driver truth table:

__  __       Inputs              |   Outputs

1G  2G | 1A1 1A2 1A3 1A4 2A1 2A2 | 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2

-------|-------------------------|------------------------

 1  1  |  X   X   X   X   X   X  |  Z   Z   Z   Z   Z   Z

 1  0  |  X   X   X   X   X   X  |  Z   Z   Z   Z  2A1 2A2

 0  1  |  X   X   X   X   X   X  | 1A1 1A2 1A3 1A4  Z   Z

 0  0  |  X   X   X   X   X   X  | 1A1 1A2 1A3 1A4 2A1 2A2


74368 (Hex Bus Driver w/3-state Out)

Hex Bus Driver truth table:

__  __       Inputs              |   Outputs

1G  2G | 1A1 1A2 1A3 1A4 2A1 2A2 | 1Y1  1Y2  1Y3  1Y4  2Y1  2Y2

-------|-------------------------|-----------------------------

 1  1  |  X   X   X   X   X   X  |  Z    Z    Z    Z    Z    Z

 1  0  |  X   X   X   X   X   X  |  Z    Z    Z    Z  '2A1 '2A2

 0  1  |  X   X   X   X   X   X  |'1A1 '1A2 '1A3 '1A4   Z    Z

 0  0  |  X   X   X   X   X   X  |'1A1 '1A2 '1A3 '1A4 '2A1 '2A2

 ' = Inverse


74373 (Octal D-type Transparent Latches)

D-latch and flip-flop truth table:

OUTPUT | ENABLE     |

enable | latch    D |  OUTPUT

-------|------------|---------

  0    |   1      1 |    1

  0    |   1      0 |    0

  0    |   0      X |    Q0

  1    |   X      X |    Z

Z = high impedance (off)


74374 (Octal D-type FF (+edge))

D latch and flip-flop truth table:

OUTPUT | ENABLE     |

ENABLE | LATCH    D |  OUTPUT

-------|------------|---------

  0    |  POS     1 |    1

  0    |  POS     0 |    0

  0    |   0      X |    Q0

  1    |   X      X |    Z

Z = high impedance (off)

POS = transition from low to high


74375 (4-bit Bistable Latches)

Bistable latch truth table:

             _

D  C  |  Q   Q

------|---------

0  1  |  0   1

1  1  |  1   0

X  0  |  Q0  Q0'


74377 (Octal D-type FF w/en)

D-type flip-flop truth table:

_                  _

G  CLK  DATA | Q   Q

-------------|------

1   X    X   | Q0  Q0'

0  POS   1   | 1   0

0  POS   0   | 0   1

X   0    X   | QO  Q0'


74378 (Hex D-type FF w/en)

D flip-flop truth table:

_                  _

G  CLK  DATA | Q   Q

-------------|------

1   X    X   | Q0  Q0'

0  POS   1   | 1   0

0  POS   0   | 0   1

X   0    X   | QO  Q0'


74379 (Quad D-type FF w/en)

D Flip-flop truth table:

 _   Inputs      |   Outputs_

 G    CLK   DATA |    Q     Q

-----------------|------------

 1     X     X   |   Q0    Q0'

 0    POS    1   |   1     0

 0    POS    0   |   0     1

 X     0     X   |   Q0    Q0'


74393 (Dual 4-bit Binary Counter)

This device features an independent active-high clear and clock input for each counter. The 74393 is ideal for practical circuits that require two independent counters that do not have to be the same count or pulsed at the same rate.

The 74393 counts from 0 to 15 in binary on every positive transition (low to high) of the clock pulse.

   Inputs  |   Output

-------------------------

CLR  CLK  |  Qd Qc Qb Qa

--------------------------

 1    X   |  0  0  0  0

 0   POS  |    Count

 0   POS  |    Count


74395 (4-bit Cascadable Shift Reg w/3-state Out)

This device is a 4-bit shift register with 3-state outputs. It features parallel-in and parallel out registers.

__ ___     __

OC CLR  LD/SH CLK  SER  A  B  C  D  |  QA  QB  QC  QD  QD'

------------------------------------|---------------------

L   X     X    X    X   X  X  X  X  |  Z   Z   Z   Z   QD'

H   L     X    X    X   X  X  X  X  |  L   L   L   L   L

H   H     H    H    X   X  X  X  X  |  NO CHANGE

H   H     H    NEG  X   A  B  C  D  |  QA  QB  QC  QD  QD

H   H     L    H    X   X  X  X  X  |  NO CHANGE

H   H     L    NEG  H   X  X  X  X  |  H   QA  QB  QC  QC

H   H     L    NEG  L   X  X  X  X  |  L   QA  QB  QC  QC


744XX Template

The 744XX component in the parts bin is a generic IC, or template. It has no pins or labels and cannot be wired into a circuit.

To use an IC, drag the template onto the circuit window. A list of available ICs for this family appears. Select the IC you want to include in your circuit. The correct graphic will appear containing labels and pins.

The 744XX template includes:

74445 (BCD-to-Decimal Dec)

74465 (Octal BUFFER w/3-state Out)

74466 (Octal BUFFER w/3-state Out)


74445 (BCD-to-Decimal Dec)

BCD to Decimal truth table:

     |  INPUTS   |      OUTPUTS

 No. |  D C B A  | 0 1 2 3 4 5 6 7 8 9

 ----|-----------|---------------------

  O  |  0 0 0 0  | 0 1 1 1 1 1 1 1 1 1

  1  |  0 0 0 1  | 1 0 1 1 1 1 1 1 1 1

  2  |  0 0 1 0  | 1 1 0 1 1 1 1 1 1 1

  3  |  0 0 1 1  | 1 1 1 0 1 1 1 1 1 1

  4  |  0 1 0 0  | 1 1 1 1 0 1 1 1 1 1

 ----|-----------|---------------------

  5  |  0 1 0 1  | 1 1 1 1 1 0 1 1 1 1

  6  |  0 1 1 0  | 1 1 1 1 1 1 0 1 1 1

  7  |  0 1 1 1  | 1 1 1 1 1 1 1 0 1 1

  8  |  1 0 0 0  | 1 1 1 1 1 1 1 1 0 1

  9  |  1 0 0 1  | 1 1 1 1 1 1 1 1 1 0

  ---|-----------|---------------------

  I  |  1 0 1 0  | 1 1 1 1 1 1 1 1 1 1

  N  |  1 0 1 1  | 1 1 1 1 1 1 1 1 1 1

  V  |  1 1 0 0  | 1 1 1 1 1 1 1 1 1 1

  A  |  1 1 0 1  | 1 1 1 1 1 1 1 1 1 1

  L  |  1 1 1 0  | 1 1 1 1 1 1 1 1 1 1

  I  |  1 1 1 1  | 1 1 1 1 1 1 1 1 1 1

  D  |


74465 (Octal BUFFER w/3-state Out)

Octal Buffers truth table:

 __ __         Inputs            |        Outputs

 G1 G2 | A1 A2 A3 A4 A5 A6 A7 A8 | Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8

-------|-------------------------|------------------------

 0  0  |  X  X  X  X  X  X  X  X | A1 A2 A3 A4 A5 A6 A7 A8

 X  X  |  X  X  X  X  X  X  X  X | Z  Z  Z  Z  Z  Z  Z  Z

- Z = High impedance (off)


74466 (Octal BUFFER w/3-state Out)

Octal Buffers truth table:

 __ __         Inputs            |        Outputs

 G1 G2 | A1 A2 A3 A4 A5 A6 A7 A8 |  Y1  Y2  Y3  Y4  Y5  Y6  Y7  Y8

-------|-------------------------|--------------------------------

 0  0  |  X  X  X  X  X  X  X  X | 'A1 'A2 'A3 'A4 'A5 'A6 'A7 'A8

 X  X  |  X  X  X  X  X  X  X  X |  Z   Z   Z   Z   Z   Z   Z   Z

- Z = High impedance (off)

- ' = Inverse


4009 (Hex INVERTER)

This device contains six independent INVERTER gates.

INVERTER gate truth table:

 A | Y

-------

 0 | 1

 1 | 0


4010 (Hex BUFFER)

This device contains six independent BUFFER gates.

BUFFER gate truth table:

 A | Y

-------

 0 | 0

 1 | 1


4XXX Series ICs

The 4XXX component in the parts bin is a generic IC, or template. It has no pins or labels and cannot be wired into a circuit.

To use an IC, drag the template onto the circuit window. A list of available ICs for this family appears. Select the IC you want to include in your circuit. The correct graphic will appear containing labels and pins.

The 4XXX template includes:

4000 (Dual 3-In NOR and INVERTER)

4001 (Quad 2-In NOR)

4002 (Dual 4-In NOR)

4008 (4-bit Binary Full Adder)

4009(Hex INVERTER)

4010(Hex BUFFER)

4011 (Quad 2-In NAND)

4012 (Dual 4-In NAND)

4013 (Dual D-type FF (+edge))

4014 (8-bit Static Shift Reg)

4015 (Dual 4-bit Static Shift Reg)

4017 (5-stage Johnson Counter)

4019 (Quad 2-In MUX)

4023 (Tri 3-In NAND)

4024 (7-stage Binary Counter)

4025 (Tri 3-In NOR)

4027 (Dual JK FF (+edge, pre, clr))

4028 (1-of-10 Dec)

4030 (Quad 2-In XOR )

4040 (12-stage Binary Counter)

4041 (Quad True/Complement BUFFER)

4042 (Quad D-latch)

4043 (Quad RS latch w/3-state Out)

4044 (Quad RS latch w/3-state Out)

4049 (Hex INVERTER)

4050 (Hex BUFFER)

4066 (Quad Analog Switches)

4068 (8-In NAND)

4069 (Hex INVERTER)

4070 (Quad 2-In XOR)

4071 (Quad 2-In OR)

4072 (Dual 4-In OR)

4073 (Tri 3-In AND)

4075 (Tri 3-In OR)

4076 (Quad D-type Reg w/3-state Out)

4077 (Quad 2-In XNOR)

4078 (8-In NOR)

4081 (Quad 2-In AND)

4082 (Dual 4-In AND)

4085 (Dual 2-Wide 2-In AND-OR-INVERTER)

4086 (4-Wide 2-In AND-OR-INVERTER)

4093 (Quad 2-In NAND (Schmitt))

4502 (Strobed hex INVERTER)

4503 (Tri-state hex BUFFER w/Strobe)

4508 (Dual 4-bit latch)

4510 (BCD up/down Counter)

4511(BCD to Seven-Segment latch/Dec)

4512 (8-In MUX w/3-state Out)

4514 (1-of-16 Dec/DEMUX w/Input latches)

4515 (1-of-16 Dec/DEMUX w/Input latches)

4516 (Binary up/down Counter)

4518 (Dual BCD Counter)

4520 (Dual Binary Counter)

4532 (8-bit priorIty Enc)

4556 (Dual 1-of-4 Dec/DEMUX)

40106 (Hex INVERTER (Schmitt))


4000 (Dual 3-In NOR and INVERTER)

NOR gate truth table:

I1 I2 I3 | O1

--------------

1  X  X  |  0

X  1  X  |  0

X  X  1  |  0

0  0  0  |  1


4019 (Quad 2-In MUX)

This device contains four 2-input multiplexers.

SELECT  INPUTS  OUTPUT

Sa  Sb  A0  B0 |  O0

---------------|------

L   L   X   X  |  L

H   L   L   X  |  L

H   L   H   X  |  H

L   H   X   L  |  L

L   H   X   H  |  H

H   H   H   X  |  H

H   H   X   H  |  H

H   H   L   L  |  L


4042 (Quad D-latch)

This device contains four independent D-latches.

D-latch truth- table:

__

En  E1  Dn | On

-----------|---------

L   L   X  | Dn

L   H   X  | Latched

H   L   X  | Latched

H   H   X  | Dn


4043 (Quad RS latch w/3-state Out)

This device contains four independent RS-latches with 3-state outputs.

RS-latch truth- table:

EO  Sn  Rn | On

-----------|----

L   X   X  | Z

H   L   H  | L

H   H   X  | H

H   L   L  | Latched


4044 (Quad RS latch w/3-state Out)

This device contains four independent RS-latches with 3-state outputs.

RS-latch truth- table:

    __  __

EO  Sn  Rn | On

-----------|----

L   X   X  | Z

H   L   H  | H

H   X   L  | L

H   H   H  | Latched


4075 (Tri 3-In OR)

This device contains three independent 3-input OR gates.

OR gate truth-table.

A  B  C | Y

--------|---

0  0  0 | 0

0  0  1 | 1

0  1  0 | 1

0  1  1 | 1

1  0  0 | 1

1  0  1 | 1

1  1  0 | 1

1  1  1 | 1


4076 (Quad D-type Reg w/3-state Out)

This device contains four independent D-type registers with 3-state outputs.

D-type register truth- table:

       INPUTS            OUTPUTS

MR  CP   ED0  ED1  Dn |    On

----------------------|-----------

H   X    X    X    X  |  L

L   POS  H    X    X  |  NO CHANGE

L   POS  X    H    X  |  NO CHANGE

L   POS  L    L    H  |  H

L   POS  L    L    L  |  L

L   NEG  X    X    X  |  NO CHANGE


4077 (Quad 2-In XNOR)

This device contains four independent 2-input EXCLUSIVE-NOR gates.

EXCLUSIVE-NOR gate truth-table:

An  Bn |  On

-------|-----

L   L  |  H

L   H  |  L

H   L  |  L

H   H  |  H


4093 (Quad 2-In NAND (Schmitt))

This device contains four independent 2-input NAND gates. Due the to the Schmitt-trigger action, this device is ideal for circuits that are susceptible to unwanted small signals, such as noise.

NAND gate truth-table:

 A | B | Y

---|---|---

 0 | 0 | 1

 0 | 1 | 1

 1 | 0 | 1

 1 | 1 | 0


4502 (Strobed hex INVERTER)

This device contains six independent INVERTER gates.

INVERTER gate truth-table:

    _   __

Dn  E   EO | On

-----------|----

L   L   L  | H

H   L   L  | L

X   H   L  | L

X   X   H  | Z


4508 (Dual 4-bit latch)

This device contains two independent 4-bit latches.

4-bit latch truth-table:

       INPUTS       OUTPUTS

MR  ST   EO   Dn |    On

-----------------|-----------

L   H    L    H  |  H

L   H    L    L  |  L

L   L    L    X  |  LATCHED

H   X    L    X  |  L

X   X    H    X  |  Z


4510 (BCD up/down Counter)

BCD up/down counter truth table:

           __

MR  PL  UP/DN  CE  CP  |   MODE

-----------------------|-----------

L   H    X    X    X   |  PARALLEL LOAD

L   L    X    H    X   |  NO CHANGE

L   L    L    L    POS |  COUNT DOWN

L   L    H    L    POS |  COUNT UP

H   X    X    X    X   |  RESET


4520 (Dual Binary Counter)

This device contains two independent binary counters.

      __

CP0   CP1   MR |        MODE

---------------|------------------

POS   1     0  |  COUNTER ADVANCES

0     NEG   0  |  COUNTER ADVANCES

NEG   X     0  |  NO CHANGE

X     POS   0  |  NO CHANGE

POS   0     0  |  NO CHANGE

1     NEG   0  |  NO CHANGE

X     X     1  |  O0 TO O3 = LOW


4556 (Dual 1-of-4 Dec/DEMUX)

This device contains two independent 1-of-4 decoders/demultiplexers.

 INPUTS         OUTPUTS

_             __  __  __  __

E  A0  A1  |  O0  O1  O2  O3

-----------|----------------

L  L   L   |  L   H   H   H

L  H   L   |  H   L   H   H

L  L   H   |  H   H   L   H

L  H   H   |  H   H   H   L

H  X   X   |  H   H   H   H


4001 (Quad 2-In NOR)

This device contains four independent 2-input NOR gates.

NOR gate truth table:

 I1  I2 | O1

------------

 1    X | 0

 X    1 | 0

 0    0 | 1


4002 (Dual 4-In NOR)

This device contains four independent 4-input NOR gates.

NOR gate truth table:

 I1 I2 I3 I4 | O1

-----------------

 1  X  X  X  | 0

 X  1  X  X  | 0

 X  X  1  X  | 0

 X  X  X  1  | 0

 0  0  0  0  | 1


4011 (Quad 2-In NAND)

This device contains four independent 2-input NAND gates.

NAND gate truth table:

 I1  I2 | O1

------------

 1   1  | 0

 0   X  | 1

 X   0  | 1


4012 (Dual 4-In NAND)

This device contains four independent 4-input NAND gates.

NAND gate truth table:

    Inputs   |   Output

 I1 I2 I3 I4 |     O1

-------------|----------

 1  1  1  1  |     0

 0  X  X  X  |     1

 X  0  X  X  |     1

 X  X  0  X  |     1

 X  X  X  0  |     1


4013 (Dual D-type FF (+edge))

D-type positive-edge-triggered flip-flop truth table:

 ___ ___            _

 SD   CD  CP D | O  O

---------------------

  0   1   X  X | 0  1

  1   0   X  X | 1  0

  1   1   X  X | 1  1

  0   0  POS 0 | 0  1

  0   0  POS 1 | 1  0

POS = positive-edge-triggered


4015 (Dual 4-bit Static Shift Reg)

This device contains two independent 4-bit static shift registers.

n  CP D   MR | O0 O1 O2 O3

-------------|-------------

1  P  D1  L  | D1 X  X  X

2  P  D2  L  | D2 D1 X  X

3  P  D3  L  | D3 D2 D1 X

4  P  D4  L  | D4 D3 D2 D1

   N  X   L  |  no change

   X  X   H  | L  L  L  L

H  = HIGH state (the more positive voltage)

L  = LOW state (the less positive voltage)

X  = state is immaterial

P  = positive-going transition

N  = negative-going transition

Dn = either HIGH or LOW

n  = number of clock pulse transitions


4017 (5-stage Johnson Counter)

5-Stage Johnson Counter truth table:

MR CP0 CP1 | operation

---------------------------

H  X  X    | O0 = O5-9 = H;O1 to O9 = L

L  H  N    | Counter advances

L  P  L    | Counter advances

L  L  X    | No change

L  X  H    | No change

L  H  P    | No change

L  N  L    | No change

H  = HIGH state (the more positive voltage)

L  = LOW state (the less positive voltage)

X  = state is immaterial

P  = positive-going transition

N  = negative-going transition

n  = number of clock pulse transitions


4023 (Tri 3-In NAND)

This device contains three independent 3-input NAND gates.

NAND gate truth table:

 I1  I2  I3 | O1

----------------

 1   1   1  |  0

 0   X   X  |  1

 X   0   X  |  1

 X   X   0  |  1


4025 (Tri 3-In NOR)

This device contains three independent 3-input NOR gates.

NOR gate truth table:

 I1 I2 I3 | O1

--------------

 1  X  X  |  0

 X  1  X  |  0

 X  X  1  |  0

 0  0  0  |  1


4028 (1-of-10 Dec)

1-of-10 Decoder truth-table:

    | BCD Inputs |   Decimal Outputs

 No.| A3 A2 A1 A0| O0 O1 O2 O3 O4 O5 O6 O7 O8 O9

----|------------|------------------------------

  0 |  0 0 0 0   | 1  0  0  0  0  0  0  0  0  0

  1 |  0 0 0 1   | 0  1  0  0  0  0  0  0  0  0

  2 |  0 0 1 0   | 0  0  1  0  0  0  0  0  0  0

  3 |  0 0 1 1   | 0  0  0  1  0  0  0  0  0  0

  4 |  0 1 0 0   | 0  0  0  0  1  0  0  0  0  0

  --|------------|------------------------------

  5 |  0 1 0 1   | 0  0  0  0  0  1  0  0  0  0

  6 |  0 1 1 0   | 0  0  0  0  0  0  1  0  0  0

  7 |  0 1 1 1   | 0  0  0  0  0  0  0  1  0  0

  8 |  1 0 0 0   | 0  0  0  0  0  0  0  0  1  0

  9 |  1 0 0 1   | 0  0  0  0  0  0  0  0  0  1

  --|------------|------------------------------

  *Extraordinary states

    |  1 0 1 0   | 0  0  0  0  0  0  0  0  0  0

    |  1 0 1 1   | 0  0  0  0  0  0  0  0  0  0

    |  1 1 0 0   | 0  0  0  0  0  0  0  0  0  0

    |  1 1 0 1   | 0  0  0  0  0  0  0  0  0  0

    |  1 1 1 0   | 0  0  0  0  0  0  0  0  0  0

    |  1 1 1 1   | 0  0  0  0  0  0  0  0  0  0


4030 (Quad 2-In XOR )

This device contains four independent 2-input EXCLUSIVE-OR gates.

EXCLUSIVE-OR gate truth-table:

 I1  I2 | O1

------------

 0   0  | 0

 0   1  | 1

 1   0  | 1

 1   1  | 0


4040 (12-stage Binary Counter)

12-stage binary counter truth table:

 __

 CP MR |     O0-O11

-------------------------

N  N   | Counter advances

N  H   | L

H  = HIGH state (the more positive voltage)

L  = LOW state (the less positive voltage)

N  = negative-going transition


4049 (Hex INVERTER)

This device contains six independent INVERTER gates.

INVERTER gate truth table:

 I1 | O1

--------

 1  | 0

 0  | 1


4066 (Quad Analog Switches)

When the C input is high, the input/outputs A and B, will pass either Digital or Analog signals in either direction.

  C | A B

----|-----

  L |  Z

  H | <->


4068 (8-In NAND)

NAND gate truth table:

 Inputs I0 through I7 | O1

----------------------|---

 All inputs 1         | 0

 One or more inputs 0 | 1


4070 (Quad 2-In XOR)

This device contains four independent 2-input EXCLUSIVE-OR gates.

EXCLUSIVE-OR gate truth table:

 A  B | Y

------|---

 0  0 | 0

 0  1 | 1

 1  0 | 1

 1  1 | 0


4071 (Quad 2-In OR)

This device contains four independent 2-input OR gates.

OR gate truth table:

 A  B | Y

----------

 1  X | 1

 X  1 | 1

 0  0 | 0


4073 (Tri 3-In AND)

This device contains three independent 3-input AND gates.

AND gate truth table:

 A  B  C | Y

-------------

 1  1  1 | 1

 0  X  X | 0

 X  0  X | 0

 X  X  0 | 0


4081 (Quad 2-In AND)

This device contains four independent 2-input AND gates.

AND gate truth table:

 A  B | Y

----------

 1  1 | 1

 0  X | 0

 X  0 | 0


4024 (7-stage Binary Counter)

The 4024 is a 7-stage binary ripple counter. A high on MR (Master Reset) forces all counter stages and outputs low.

The 4024 counts from 0 to 15 in binary on every negative (high to low) transition of the clock pulse.

  Inputs  |      Output

---------------------------------

 MR   CP  | Qg Qf Qe Qd Qc Qb Qa

---------------------------------

 1    X   | 0  0  0  0  0  0  0

 0   NEG  |       Count

 0   NEG  |       Count


4027 (Dual JK FF (+edge, pre, clr))

This device contains two independent JK flip-flops. They have separate preset and clear inputs.

JK flip-flop truth table:

                       _

  SD CD CP J  K | On   On

------------------------

  1  0  X  X  X | 1    0

  0  1  X  X  X | 0    1

  1  1  X  X  X | 1    1

  0  0  P  0  0 |  Hold

  0  0  P  1  0 | 1    0

  0  0  P  0  1 | 0    1

  0  0  P  1  1 | Toggle

P = triggers on POSITIVE pulse


4041 (Quad True/Complement BUFFER)

Provides both inverted and non-inverted buffered outputs for each input.

     INPUTS                   OUTPUTS

                    __      __      __      __

 I1  I2  I3  I4  |  O1  O2  O3  O4  O5  O6  O7  O8

-----------------|--------------------------------

                 |  __      __      __      __

 X   X   X   X   |  I1  I1  I2  I2  I3  I3  I4  I4


4050 (Hex BUFFER)

This device contains six independent BUFFER/non-inverting gates.

BUFFER gate truth table:

 A | Y

---|---

 0 | 0

 1 | 1


4069 (Hex INVERTER)

This device contains six independent INVERTER gates.

INVERTER gate truth table:

If one or more inputs is high, the output is high.

If all inputs are low, the output is low.

 A | Y

---|---

 0 | 1

 1 | 0


4072 (Dual 4-In OR)

4-input OR gate truth table:

   INPUTS    OUTPUT

A  B  C  D  |  Y

-------------------

0  0  0  0  |  0

0  0  0  1  |  1

0  0  1  0  |  1

0  0  1  1  |  1

0  1  0  0  |  1

0  1  0  1  |  1

0  1  1  0  |  1

0  1  1  1  |  1

1  0  0  0  |  1

1  0  0  1  |  1

1  0  1  0  |  1

1  0  1  1  |  1

1  1  0  0  |  1

1  1  0  1  |  1

1  1  1  0  |  1

1  1  1  1  |  1

Simplified 4-input OR gate truth table:

A  B  C  D  |  Y

--------------------

0  0  0  0  |  0

1  X  X  X  |  1

X  1  X  X  |  1

X  X  1  X  |  1

X  X  X  1  |  1


4078 (8-In NOR)

8-input NOR gate simplified truth table:

If one or more inputs are high, the output is low.

            INPUTS               OUTPUT

 I0  I1  I2  I3  I4  I5  I6  I7 |  O1

--------------------------------|-----

 0   0   0   0   0   0   0   0  |  1

 1   X   X   X   X   X   X   X  |  0

 X   1   X   X   X   X   X   X  |  0

 X   X   1   X   X   X   X   X  |  0

 X   X   X   1   X   X   X   X  |  0

 X   X   X   X   1   X   X   X  |  0

 X   X   X   X   X   1   X   X  |  0

 X   X   X   X   X   X   1   X  |  0

 X   X   X   X   X   X   X   1  |  0


4082 (Dual 4-In AND)

This device contains two independent 4-input AND gates.

All 4-inputs on each 4-input gate must be high to obtain a high at the output.

A  B  C  D  |  Y

-------------------

0  0  0  0  |  0

0  0  0  1  |  0

0  0  1  0  |  0

0  0  1  1  |  0

0  1  0  0  |  0

0  1  0  1  |  0

0  1  1  0  |  0

0  1  1  1  |  0

1  0  0  0  |  0

1  0  0  1  |  0

1  0  1  0  |  0

1  0  1  1  |  0

1  1  0  0  |  0

1  1  0  1  |  0

1  1  1  0  |  0

1  1  1  1  |  1


40106 (Hex INVERTER (Schmitt))

This device contains six independent INVERTER gates. Due the to the Schmitt-trigger action, this device is ideal for circuits that are susceptible to unwanted small signals, such as noise.

INVERTER gate truth-table:

 A | Y

---|---

 0 | 1

 1 | 0


4503 (Tri-state hex BUFFER w/Strobe)

Four of these six non-inverting buffers (I1 through I4) are enabled by a high on EN1 and the last two (I5 and I6) are enabled by a high on EN2.

             INPUTS                        OUTPUTS

                          ENABLE

 I1  I2  I3  I4  I5  I6   EN1 EN2 | O1  O2  O3  O4  O5  O6

----------------------------------|-----------------------

 X   X   X   X   X   X  |  1   1  | I1  I2  I3  I4  I5  I6

 X   X   X   X   X   X  |  0   1  | Z   Z   Z   Z   I5  I6

 X   X   X   X   X   X  |  1   0  | I1  I2  I3  I4  Z   Z

 X   X   X   X   X   X  |  0   0  | Z   Z   Z   Z   Z   Z

Z = High impedance

X = Irrelevant


4512 (8-In MUX w/3-state Out)

This device is a 8-input multiplexer with 3-state outputs.

                     INPUTS                       OUTPUT

_   _     Select                Data

EO  E    C  B  A   I0  I1  I2  I3  I4  I5  I6  I7|  O

-------|---------|-------------------------------|-----

0   1  | X  X  X | X   X   X   X   X   X   X   X |  0

0   0  | 0  0  0 | 0   X   X   X   X   X   X   X |  0

0   0  | 0  0  0 | 1   X   X   X   X   X   X   X |  1

0   0  | 0  0  1 | X   0   X   X   X   X   X   X |  0

0   0  | 0  0  1 | X   1   X   X   X   X   X   X |  1

0   0  | 0  1  0 | X   X   0   X   X   X   X   X |  0

0   0  | 0  1  0 | X   X   1   X   X   X   X   X |  1

0   0  | 0  1  1 | X   X   X   0   X   X   X   X |  0

0   0  | 0  1  1 | X   X   X   1   X   X   X   X |  1

0   0  | 1  0  0 | X   X   X   X   0   X   X   X |  0

0   0  | 1  0  0 | X   X   X   X   1   X   X   X |  1

0   0  | 1  0  1 | X   X   X   X   X   0   X   X |  0

0   0  | 1  0  1 | X   X   X   X   X   1   X   X |  1

0   0  | 1  1  0 | X   X   X   X   X   X   0   X |  0

0   0  | 1  1  0 | X   X   X   X   X   X   1   X |  1

0   0  | 1  1  1 | X   X   X   X   X   X   X   0 |  0

0   0  | 1  1  1 | X   X   X   X   X   X   X   1 |  1

1   X  | X  X  X | X   X   X   X   X   X   X   X |  Z

__

EO = Output Enable (Active-low)

_

E = Enable input (Active-low)

Z = High impedance


4514 (1-of-16 Dec/DEMUX w/Input latches)

This device is a 1-of-16 decoder/demultiplexer with input latches. The input latches allow for the user to hold a previous input with the enable input while the inputs change.

1-of-16 decoder/demultiplexer truth-table:

 _

 E  A3 A2 A1 A0 |  O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15

 ---------------|-------------------------------------------------------

 1  X  X  X  X  |  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0

 0  0  0  0  0  |  1  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0

 0  0  0  0  1  |  0  1  0  0  0  0  0  0  0  0   0   0   0   0   0   0

 0  0  0  1  0  |  0  0  1  0  0  0  0  0  0  0   0   0   0   0   0   0

 0  0  0  1  1  |  0  0  0  1  0  0  0  0  0  0   0   0   0   0   0   0

 0  0  1  0  0  |  0  0  0  0  1  0  0  0  0  0   0   0   0   0   0   0

 0  0  1  0  1  |  0  0  0  0  0  1  0  0  0  0   0   0   0   0   0   0

 0  0  1  1  0  |  0  0  0  0  0  0  1  0  0  0   0   0   0   0   0   0

 0  0  1  1  1  |  0  0  0  0  0  0  0  1  0  0   0   0   0   0   0   0

 0  1  0  0  0  |  0  0  0  0  0  0  0  0  1  0   0   0   0   0   0   0

 0  1  0  0  1  |  0  0  0  0  0  0  0  0  0  1   0   0   0   0   0   0

 0  1  0  1  0  |  0  0  0  0  0  0  0  0  0  0   1   0   0   0   0   0

 0  1  0  1  1  |  0  0  0  0  0  0  0  0  0  0   0   1   0   0   0   0

 0  1  1  0  0  |  0  0  0  0  0  0  0  0  0  0   0   0   1   0   0   0

 0  1  1  0  1  |  0  0  0  0  0  0  0  0  0  0   0   0   0   1   0   0

 0  1  1  1  0  |  0  0  0  0  0  0  0  0  0  0   0   0   0   0   1   0

 0  1  1  1  1  |  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   1


4515 (1-of-16 Dec/DEMUX w/Input latches)

This device is a 1-of-16 decoder/demultiplexer with input latches. The input latches allow for the user to hold a previous input with the enable input while the inputs change.

1-of-16 decoder/demultiplexer truth-table:

_

E  A3 A2 A1 A0 |  O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15

---------------|-------------------------------------------------------

1  X  X  X  X  |  1  1  1  1  1  1  1  1  1  1   1   1   1   1   1   1

0  0  0  0  0  |  0  1  1  1  1  1  1  1  1  1   1   1   1   1   1   1

0  0  0  0  1  |  1  0  1  1  1  1  1  1  1  1   1   1   1   1   1   1

0  0  0  1  0  |  1  1  0  1  1  1  1  1  1  1   1   1   1   1   1   1

0  0  0  1  1  |  1  1  1  0  1  1  1  1  1  1   1   1   1   1   1   1

0  0  1  0  0  |  1  1  1  1  0  1  1  1  1  1   1   1   1   1   1   1

0  0  1  0  1  |  1  1  1  1  1  0  1  1  1  1   1   1   1   1   1   1

0  0  1  1  0  |  1  1  1  1  1  1  0  1  1  1   1   1   1   1   1   1

0  0  1  1  1  |  1  1  1  1  1  1  1  0  1  1   1   1   1   1   1   1

0  1  0  0  0  |  1  1  1  1  1  1  1  1  0  1   1   1   1   1   1   1

0  1  0  0  1  |  1  1  1  1  1  1  1  1  1  0   1   1   1   1   1   1

0  1  0  1  0  |  1  1  1  1  1  1  1  1  1  1   0   1   1   1   1   1

0  1  0  1  1  |  1  1  1  1  1  1  1  1  1  1   1   0   1   1   1   1

0  1  1  0  0  |  1  1  1  1  1  1  1  1  1  1   1   1   0   1   1   1

0  1  1  0  1  |  1  1  1  1  1  1  1  1  1  1   1   1   1   0   1   1

0  1  1  1  0  |  1  1  1  1  1  1  1  1  1  1   1   1   1   1   0   1

0  1  1  1  1  |  1  1  1  1  1  1  1  1  1  1   1   1   1   1   1   0


4516 (Binary up/down Counter)

This binary up/down counter counts from 0000 to 1111 in binary (0 to 15 in decimal).

Binary up/down counter truth table:

          __  __  __

MR  PL UP/DN  CE  CP         MODE

-----------------------|--------------

0   1    X    X   X    | PARALLEL LOAD

0   0    X    H   X    | NO CHANGE

0   0    L    L   POS  | COUNT DOWN

0   0    H    L   POS  | COUNT UP

1   X    X    X   X    | RESET


4518 (Dual BCD Counter)

This device contains two independent BCD counters.

       ___

 CP0   CP1   MR |        MODE

----------------|------------------

 POS   1     0  |  COUNTER ADVANCES

 0     NEG   0  |  COUNTER ADVANCES

 NEG   X     0  |  NO CHANGE

 X     POS   0  |  NO CHANGE

 POS   0     0  |  NO CHANGE

 1     NEG   0  |  NO CHANGE

 X     X     1  |  O0 TO O3 = LOW


4532 (8-bit Priority Enc)

This device is an 8-bit priority encoder.

 E1 0 1 2 3 4 5 6 7  |  GS O2 O1 O0 EO

---------------------|----------------

 0  X X X X X X X X  |  0  0  0  0  0

 1  0 0 0 0 0 0 0 0  |  0  0  0  0  1

 1  1 X X X X X X X  |  1  1  1  1  0

 1  0 1 X X X X X X  |  1  1  1  0  0

 1  0 0 1 X X X X X  |  1  1  0  1  0

 1  0 0 0 1 X X X X  |  1  1  0  0  0

 1  0 0 0 0 1 X X X  |  1  0  1  1  0

 1  0 0 0 0 0 1 X X  |  1  0  1  0  0

 1  0 0 0 0 0 0 1 X  |  1  0  0  1  0

 1  0 0 0 0 0 0 0 1  |  1  0  0  0  0


74150 (1-of-16 Data Sel/MUX)

This device can select one of sixteen data sources when a 4-bit binary number is applied to the inputs. It is equipped with one enable input and a complementary output.

    Inputs _  Output

 D C B A   G |  W

---------|---|------

 X X X X | H |  H

         |   |  __

 0 0 0 0 | L |  EO

         |   |  __

 0 0 0 1 | L |  E1

         |   |  __

 0 0 1 0 | L |  E2

         |   |  __

 0 0 1 1 | L |  E3

         |   |  __

 0 1 0 0 | L |  E4

         |   |  __

 0 1 0 1 | L |  E5

         |   |  __

 0 1 1 0 | L |  E6

         |   |  __

 0 1 1 1 | L |  E7

         |   |  __

 1 0 0 0 | L |  E8

         |   |  __

 1 0 0 1 | L |  E9

         |   |  ___

 1 0 1 0 | L |  E10

         |   |  ___

 1 0 1 1 | L |  E11

         |   |  ___

 1 1 0 0 | L |  E12

         |   |  ___

 1 1 0 1 | L |  E13

         |   |  ___

 1 1 1 0 | L |  E14

         |   |  ___

 1 1 1 1 | L |  E15


7439 (Quad 2-In NAND (LS-OC))

This device contains four independent 2-input NAND gates. For correct performance, the open collector outputs require pull-up resistors. For this IC, we recommend the LS-OC model for realistic performance.

NAND gate truth table:

A  B | Y

-----|---

1  1 | 0

0  X | 1

X  0 | 1


74166 (Parallel-load 8-bit Shift Reg)

This shift-register is a parallel-in or serial-in, serial out device. It shifts the data in the direction of QA toward QH when clocked. It features an active-low clear input. To load the data at the 8-inputs into the device, apply a low level at the shift/load input.

                           INPUTS                   INTERNAL  |

      SHIFT/                            PARALLEL  | __O/P __  |OUTPUTS

CLR|  LOAD   |CLK INH | CLK | SERIAL | A through H| QA    QB  |  QH

---|---------|--------|-----|--------|------------|-----------|----

 0 |    X    |    X   |  X  |    X   | X  X  X  X |  L     L  |   L

 1 |    X    |    0   |  0  |    X   | X  X  X  X | QA0   QB0 |  QH0

 1 |    0    |    0   | POS |    X   |   A TO H   |  a     b  |   H

 1 |    1    |    0   | POS |    1   | X  X  X  X |  1    QAn |  QGn

 1 |    1    |    0   | POS |    0   | X  X  X  X |  0    QAn |  QGn

 1 |    X    |    1   | POS |    X   | X  X  X  X | QA0   QB0 |  QH0

POS = transition from low to high

a, b, c, d = the level of steady state input at A, B, C, or D respectively


4008 (4-bit Binary Full Adder)

This device is capable of adding two 4-bit binary numbers together.

4-bit binary adder truth table:

     INPUTS   OUTPUTS

 CIN   A   B |COUT| S

-----|---|---|----|---

  0  | 0 | 0 | 0  | 0

  0  | 0 | 1 | 0  | 1

  0  | 1 | 0 | 0  | 1

  0  | 1 | 1 | 1  | 0

  1  | 0 | 0 | 0  | 1

  1  | 0 | 1 | 1  | 0

  1  | 1 | 0 | 1  | 0

  1  | 1 | 1 | 1  | 1


4014 (8-bit Static Shift Reg)

This device is an 8-bit synchronous static shift register with 8 parallel inputs, a serial data input and a parallel enable input.

Serial Operation:

                 INPUTS                 OUTPUTS

 n PE DS >CLK P0 P1 P2 P3 P4 P5 P6 P7 | O5 O6 O7

--------------------------------------|----------

 1 L  D1  POS X  X  X  X  X  X  X  X  | X  X  X

 2 L  D2  POS X  X  X  X  X  X  X  X  | X  X  X

 3 L  D3  POS X  X  X  X  X  X  X  X  | X  X  X

 4 L  D4  POS X  X  X  X  X  X  X  X  | X  X  X

 5 L  D5  POS X  X  X  X  X  X  X  X  | X  X  X

 6 L  D6  POS X  X  X  X  X  X  X  X  | D1 X  X

 7 L  D7  POS X  X  X  X  X  X  X  X  | D2 D1 X

 9 L  D8  POS X  X  X  X  X  X  X  X  | D3 D2 D1

10 L  D9  POS X  X  X  X  X  X  X  X  | D4 D3 D2

 X X  X   NEG X  X  X  X  X  X  X  X  | no change

Parallel operation:

               INPUTS                 OUTPUTS

 PE DS >CLK P0 P1 P2 P3 P4 P5 P6 P7 | O5 O6 O7

------------------------------------|----------

 H  X   POS X  X  X  X  X  X  X  X  | P5 P6 P7

 H  X   NEG X  X  X  X  X  X  X  X  | no change


4085 (Dual 2-Wide 2-In AND-OR-INVERTER)

This device contains a combination of gates (AND, OR and INVERTER) which produce the following output:

       INPUTS      |OUTPUT

 A0| A1| A2| A3| A4| OA

---|---|---|---|---|----

 L | L | L | L | L | H

 L | L | L | L | H | L

 L | L | L | H | L | H

 L | L | L | H | H | L

 L | L | H | L | L | H

 L | L | H | L | H | L

 L | L | H | H | L | H

 L | L | H | H | H | L

 L | H | L | L | L | L

 L | H | L | L | H | L

 L | H | L | H | L | H

 L | H | L | H | H | L

 L | H | H | L | L | H

 L | H | H | L | H | L

 L | H | H | H | L | H

 L | H | H | H | H | L

 H | L | L | L | L | L

 H | L | L | L | H | L

 H | L | L | H | L | H

 H | L | L | H | H | L

 H | L | H | L | L | H

 H | L | H | L | H | L

 H | L | H | H | L | H

 H | L | H | H | H | L

 H | H | L | L | L | L

 H | H | L | L | H | L

 H | H | L | H | L | L

 H | H | L | H | H | L

 H | H | H | L | L | L

 H | H | H | L | H | L

 H | H | H | H | L | L

 H | H | H | H | H | L


4086 (4-Wide 2-In AND-OR-INVERTER)

This device contains a combination of gates (AND, OR and INVERTER) which produce the following output:

               INPUTS                  |OUTPUT

 I0| I1| I2| I3| I4| I5| I6| I7| I8|~I9| O

---|---|---|---|---|---|---|---|---|---|----

 X | X | X | X | X | X | X | X | H | X | L

 X | X | X | X | X | X | X | X | X | L | L

 H | H | X | X | X | X | X | X | X | X | L

 X | X | H | H | X | X | X | X | X | X | L

 X | X | X | X | H | H | X | X | X | X | L

 X | X | X | X | X | X | H | H | X | X | L

   ANY OTHER COMBINATION OF INPUTS     | H


Chip Abbreviation Table

This table has been created to provide an expanded version of each short form and acronym used in the digital ICs section of this help file:

-edge -------------------------- negative edge

+edge -------------------------- positive edge

Alu ---------------------------- arithmetic logic unit

BCD ---------------------------- binary coded decimal

BUFFER ------------------------- non-inverting gate

clk ---------------------------- clock

clr ---------------------------- clear

com ---------------------------- common

Dec ---------------------------- decoder

DEMUX -------------------------- demultiplexer

dual --------------------------- 2 (two)

En ----------------------------- enable

Enc ---------------------------- encoder

EX ----------------------------- EXCLUSIVE

ff ----------------------------- flip-flop

HC-OD -------------------------- open-collector, CMOS compliant

hex ---------------------------- 6 (six)

LS-OC -------------------------- open-collector

MUX ---------------------------- multiplexer

Octal -------------------------- 8 (octal)

Out ---------------------------- output

pre ---------------------------- preset

quad --------------------------- 4 (quadruple)

Reg ---------------------------- register

RS ----------------------------- reset/set

Schmitt ------------------------ Schmitt Trigger

Sel ---------------------------- selector

sh/ld -------------------------- shift/load

shl ---------------------------- shift left

shr ---------------------------- shift right

Sync --------------------------- synchronous

tri ---------------------------- 3 (triple)

Univ.--------------------------- universal


4511(BCD to Seven-Segment latch/Dec)

The 4511 BCD (Binary-Coded Decimal)-to-seven-segment latch decoder translates a 4-bit BCD input into hexadecimal, and outputs high on the output pins corresponding to the hexadecimal representation of the BCD input. There are provisions for lamp testing and for blanking the outputs.

           Inputs                Outputs

     __  __  __

No.  EL  BI  LT   D C B A | a b c d e f g

----|---|---|---|---------|--------------

    | X | X | 0 | 0 0 0 0 | 1 1 1 1 1 1 0

    | X | 0 | 1 | 0 0 0 0 | 1 1 1 1 1 1 0

 0  | 0 | 1 | 1 | 0 0 0 0 | 1 1 1 1 1 1 0

 1  | 0 | 1 | 1 | 0 0 0 1 | 0 1 1 0 0 0 0

 2  | 0 | 1 | 1 | 0 0 1 0 | 1 1 0 1 1 0 1

 3  | 0 | 1 | 1 | 0 0 1 1 | 1 1 1 1 0 0 1

----|---|---|---|---------|--------------

 4  | 0 | 1 | 1 | 0 1 0 0 | 0 1 1 0 0 1 1

 5  | 0 | 1 | 1 | 0 1 0 1 | 1 0 1 1 0 1 1

 6  | 0 | 1 | 1 | 0 1 1 0 | 0 0 1 1 1 1 0

 7  | 0 | 1 | 1 | 0 1 1 1 | 1 1 1 0 0 0 0

----|---|---|---|---------|--------------

 8  | 0 | 1 | 1 | 1 0 0 0 | 1 1 1 1 1 1 1

 9  | 0 | 1 | 1 | 1 0 0 1 | 1 1 1 0 0 1 1

10  | 0 | 1 | 1 | 1 0 1 0 | 0 0 0 1 1 0 1  <  I

11  | 0 | 1 | 1 | 1 0 1 1 | 0 0 1 1 0 0 1  <  N

----|---|---|---|---------|--------------  <  V

12  | 0 | 1 | 1 | 1 1 0 0 | 0 1 0 0 0 1 1  <  A

13  | 0 | 1 | 1 | 1 1 0 1 | 1 0 0 1 0 1 1  <  L

14  | 0 | 1 | 1 | 1 1 1 0 | 0 0 0 1 1 1 1  <  I

15  | 0 | 1 | 1 | 1 1 1 1 | 0 0 0 0 0 0 0  <  D

    | 1 | 1 | 1 | 0 0 0 0 | DEPENDS ON PREV. STATE

__

EL  = active-low latch enable input

__

BI = active-low ripple-blanking input

___

LT  = active-low lamp-test input


Digital Parts Bin

Half Adder

Full Adder

RS Flip-Flop

JK Flip-Flop with Active High Asynchronous Inputs

JK Flip-Flop with Active Low Asynchronous Inputs

D Flip-Flop with Active Low Asynchronous Inputs

Multiplexer ICs

Demultiplexer ICs

Encoder ICs

Arithmetic ICs

Counter ICs

Shift Register ICs

Flip-Flops ICs


Half Adder

The half-adder is an arrangement of gates and inverters that performs binary addition. Two numbers can be added together, but there is no provision for including an external "carry."

To perform binary number addition, the following four rules must be followed:

 0 + 0 = 0

 1 + 0 = 1

 0 + 1 = 1

 1 + 1 = 0 and carry 1

These rules apply to any two positive binary numbers.


Full Adder

The full-adder is a modification of the half-adder that allows an external "carry" to be included in the computation.

Carry In|   A   |    B   |  Sum  | Carry Out

--------------------------------------------

  0     |   0   |    0   |   0   |     0

  0     |   0   |    1   |   1   |     0

  0     |   1   |    0   |   1   |     0

  0     |   1   |    1   |   0   |     1

  1     |   0   |    0   |   1   |     0

  1     |   0   |    1   |   0   |     1

  1     |   1   |    0   |   0   |     1

  1     |   1   |    1   |   1   |     1

See also: Half-Adder


RS Flip-Flop

The RS flip-flop  in the parts bin is an unclocked, level-triggered device.


D Flip-Flop

The D flip-flop  is triggered on the positive edge of the clock input.

See also:  D flip-flop with active low asynch inputs


JK Flip-Flop with Active Low Asynch Inputs

This JK flip-flop  is similar to the JK flip-flop with active high asynchronous inputs, except the preset and clear inputs are activated when they are pulled low.

See also: JK Flip-Flop with Active High Asnychronous Inputs


JK Flip-Flop Theory

Using a clock pulse to control the change of state of the flip-flop synchronizes its operation with the rest of the circuit. This avoids the "race condition" that can occur with the RS flip-flop. The device is triggered by the negative (falling) edge of the clock pulse.

JK flip-flop truth table:

Preset | Clear |  J  K  | Clock |  Q  Q'

-----------------------------------------

  1    |   1   |  X  X  |   X   |  1  1  (unstable)

  1    |   0   |  X  X  |   X   |  1  0

  0    |   1   |  X  X  |   X   |  0  1

  0    |   0   |  0  0  |   -   |  -  -  (no change)

  0    |   0   |  0  1  |   -   |  0  1

  0    |   0   |  1  0  |   -   |  1  0

  0    |   0   |  1  1  |   -   |  -  -  (changes to

                                          opposite)


RS Flip-Flop Theory

The RS flip-flop has an undesired operating condition, where 1 levels at both inputs will cause both outputs to go to a 0 level. This undefined condition must be avoided. Circuits involving feedback will lead to a "race condition" where the output will be unpredictable.

RS flip-flop truth table:

  S   R  |  Q  Q'

------------------

  0   0  |  -  -  (no change)

  0   1  |  0  1

  1   0  |  1  0

  1   1  |  x  x  (undefined)

RS flip-flops are not suited for sequential circuits without additional circuitry. Alone they are used for debouncing switches and holding states, such as in alarm systems.


D Flip-Flop Theory
+D Flip-Flop Theory

The D flip-flop holds the value given as its input until the input changes. It thus stores data. Since it is activated by the clock pulse, it samples the input data only when the positive (rising) edge of the clock pulse occurs.

D flip-flop truth table:

  D  C  |  Qn + 1

------------------

  0  0  |    0    (reset)

  1  1  |    1    (set)

There is another version of the D flip-flop, known as the D latch. The primary difference between the two is the "edge triggering" feature of the D flip-flop, absent in the D Latch.


D Flip-Flop with Active Low Asynch Inputs

This flip-flop is similar to the D flip-flop except it has two active low asynchronous inputs: preset and clear. These can be used to preset and clear the output and override the D and clock inputs.

See also: D Flip-Flop


Multiplexer ICs

This component is actually just a template. It has no pins or labels and cannot be wired into a circuit.

To use an IC, drag the template onto the circuit window. A list of available ICs for this family appears. Select the IC you want to include in your circuit. The correct graphic appears, containing labels and pins.

This template includes:

Generic 1-of-8 Multiplexer

74151 (Data Selector/Mux)

74153 (2 4-to-1 Data Selectors/Mux)

74157 (4 2-to-1 Data Selector/Mux)

74158 (4 2-to-1 Data Selector/Mux)

74251 (Data Selector/Mux)

74253 (2 4-to-1 Data Selector/Mux)

74257 (4 2-TO-1 Data Selector/Mux)

74258 (4 2-to-1 Data Selector/Mux)

74298 (4 2-In Mux)

74353 (2 4-to-1 Data Selector/Mux)


Generic 1-of-8 Multiplexer

The multiplexer (data selector) has twelve inputs and two outputs. The inputs include eight data lines, three control lines and one enable input. Depending on the value at the control lines, the multiplexer selects one of eight data inputs and outputs its value (high or low) at the Y output pin. The enable input (G) must be low to enable the output. W holds the complement of the Y output.


JK Flip-Flop with Active High Asynch Inputs

The JK flip-flop  is triggered at the negative edge of the clock input. Its preset and clear lines can be used to override the JK and clock inputs. It does not suffer from the "race condition" of the RS flip-flop.


Demultiplexer ICs

This component is actually just a template. It has no pins or labels and cannot be wired into a circuit.

To use an IC, drag the template onto the circuit window. A list of available ICs for this family appears. Select the IC you want to include in your circuit. The correct graphic appears, containing labels and pins.

This template includes:

Generic 8-to-1 Demultiplexer

Generic 3-to-8 Decoder

Generic B CD-to-Seven-Segment

4028 (1 of 10 decoder)

7442 (BCD to DEC decoder)

7445 (BCD to DEC decoder)

74138 (3 to 8 decoder/demux)

74139 (2 2 to 4 decoder/demux)

74145 (BCD to decimal decoders/drivers)

74154 (4 4 to 16 decoder/demux)

74155 (2 2 to 4 decoder/demux)

74156 (2 2 to 4 line decoder/demux)

74159 (4 to 16 line decoder/demux)

74445 (BCD to Decimal Decoder/Driver)


Generic 8-to-1 Demultiplexer

The generic demultiplexer has 4 inputs and 8 outputs. A low input at pin D is routed to one of the output pins as determined by the three inputs A, B, C. All of the other outputs remain high. If EN (enable) has a high input, all eight outputs are high.


Encoder ICs

This component is actually just a template. It has no pins or labels and cannot be wired into a circuit.

To use an IC, drag the template onto the circuit window. A list of available ICs for this family appears. Select the IC you want to include in your circuit. The correct graphic appears, containing labels and pins.

This template includes:

Generic 8-to-3 Encoder

74147 ( 10 to 4 line priority encoder)

74148 (8 to 3 line priority encoder)


Shift Register ICs

This component is actually just a template. It has no pins or labels and cannot be wired into a circuit.

To use an IC, drag the template onto the circuit window. A list of available ICs for this family appears. Select the IC you want to include in your circuit. The correct graphic appears, containing labels and pins.

This template includes:

Generic 4-bit Universal Shift Register

4015 (2 r bit static shift register)

7491 (8 bit shift register)

74164 (8 bit shift register)

74173 (4 bit D type register)

74194 (4 bit bidirectional shift register)

74195 (4 bit shift register)

74198 (8 bit shift register)

74199 (8 bit shift register)

74350 (4 bit shifter with 3 state outputs)


Generic 4-bit Universal Shift Register

Shift registers are interconnected flip-flops which are useful for storing data. The Electronics Workbench shift register is a 4-bit universal register with 10 inputs and 4 outputs. The shift register is capable of handling data in any of the following modes: serial-in, serial-out; parallel-in, parallel-out; shift left and shift right.

For each pulse of the clock the register shifts stored data as determined by the control pins S0 and S1.


Flip-Flop ICs

This component is actually just a template. It has no pins or labels and cannot be wired into a circuit.

To use an IC, drag the template onto the circuit window. A list of available ICs for this family appears. Select the IC you want to include in your circuit. The correct graphic appears, containing labels and pins.

This template includes:

4013 (2 D-Type Edge FF)

7472 (AND J K Master Slave FF with Pre & Clr)

7473 (2 JK FF)

7474 (2 D Type Edge FF)

7475 (4 Bit Bistable Latch)

7476 (2 JK FF)

7477 (4 Bit Bistable Latch)

74107 (2 JK FF)

74109 (2 JK Edge FF)

74112 (2 JK Edge FF)

74113 (2 JK Edge FF)

74114 (2 J K FF with Pre, Com Clr & Clk

74116 (2 Bit Latches with Clear)

74174 (6 D Type FF)

74175 (4 D Type FF)

74273 (4 Bit D Type Reg)

74373 (Oct D Type Latch and FF)

74374 (Oct D Type Latch and FF)

74375 (4 Bit Bistable Latch)

74377 (8 D Type FF)

74378 (6 D Type FF)

74379 (4 D Type FF with Enable)


Generic 8-to-3 Encoder

The encoder features priority decoding of the inputs. That is, only the highest order data line is encoded. The encoder encodes eight input lines to an octal code. All data inputs, outputs and enables are active low.


Counter ICs

This component is actually just a template. It has no pins or labels and cannot be wired into a circuit.

To use an IC, drag the template onto the circuit window. A list of available ICs for this family appears. Select the IC you want to include in your circuit. The correct graphic appears, containing labels and pins.

This template includes:

Generic 4-bit Binary Counter

4040 (12 Stage Binary Counter)

7469 (2 4 Bit Decade or Binary Counters)

7490 (Decade Counter)

7492 (12 Counters)

7493 (4 Bit Binary Counters)

74160 (Decade Counter)

74162 (Decade Counter)

74163 (4 Bit Counter)

74169 (4 Bit Up Down Counter)

74190 (Up Down Counter)

74191 (Up Down Counter)

74192 (4 Bit Up Down Counter)

74290 (Decade Counter)

74293 (4-Bit Bin Counter)


Generic 4-bit Binary Counter

The 4-bit counter has two clock inputs and four outputs. The "A" counter is essentially a shift register which transfers a high bit for each clock pulse - negative edge triggered. To use the counter's maximum count length, an external clock should be fed to the clock input CLKA and the output from QA must be connected to the clock input CLKB. The counter is reset by pulling both the RO1 or RO2 inputs low.


Arithmetic ICs

This component is actually just a template. It has no pins or labels and cannot be wired into a circuit.

To use an IC, drag the template onto the circuit window. A list of available ICs for this family appears. Select the IC you want to include in your circuit. The correct graphic appears, containing labels and pins.

This template includes:

74181 (ALU function generator)

74280 (9-bit parity generator checker)


Generic 3-to-8 Decoder

The generic decoder decodes one of eight input lines as determined by three control inputs A, B, C and two enable inputs, G1 and G2. If G1 is high and G2 low, then the output corresponding to the decimal equivalent of the binary word at the inputs is pulled low. If G1 is low or G2 is high then all outputs are high.


Generic BCD-to-Seven-Segment Decoder

The generic BCD(binary-coded decimal)-to-seven-segment decoder translates a 4-bit BCD input into hexadecimal, and outputs high on the output pins corresponding to the hexadecimal representation of the BCD input. There are provisions for lamp testing and for blanking the outputs.


Diodes Parts Bin

Diode

Zener Diode

LED

Full Wave Bridge Rectifier

Shockley Diode

Silicon Controlled Rectifier

Diac

Triac


Diode

A diode conductselectric current very easily in one direction and very poorly in the other direction. It is the simplest form of solid-state switch, being either open (not conducting) or closed (conducting).

An ideal diode is included in the parts bin. You can specify a real-world diode by changing its model.


Diodes: Background Information

Diodes exhibit a number of useful characteristics, such as predictable capacitance (that can be voltage controlled) and a region of very stable voltage. They can, therefore, be used as voltage-controlled capacitors (varactors) and voltage references (Zener diodes).

Because diodes will conduct current easily in only one direction, they are used extensively as power rectifiers, converting AC signals to pulsating DC signals, for both power applications and radio receivers.

Diodes behave as voltage-controlled switches, and have replaced mechanical switches and relays in many applications requiring remote signal switching.

Even indicator lamps are now replaced with diodes (LEDs) that emit light in a variety of colors when conducting.

A special form of diode, called a Zener diode, is useful for voltage regulation.

See also:

Capacitor

Zener Diode

LED


Zener Diode

Zener diodes are special diodes designed to continue operation within the reverse breakdown or Zener region, beyond the peak inverse voltage rating of normal diodes. This reverse breakdown voltage is called the Zener test voltage (Vzt), which can range between 2.4 V and 200 V.

Zener diodes are used primarily for voltage regulation.


LED

The LED (light-emitting diode) emits visible light when conducting current in the "forward" direction (when the current exceeds Ion, in amps).

An ideal LED is included in the parts bin, but you can specify a different model.


LED: Background Information

LEDs are constructed of gallium arsenide or gallium arsenide phosphide. While efficiency can be obtained when conducting as little as 2 milliamperes of current, the usual design goal is in the vicinity of 10 mA. During conduction, there is a voltage drop across the diode of about 2 volts.

Most early information display devices required power supplies in excess of 100 volts. The LED ushered in an era of information display components with sizes and operating voltages compatible with solid-state electronics. Until the low-power liquid-crystal display was developed, LED displays were common, despite high current demands, in battery-powered instruments, calculators and watches. They are still commonly used as on-board annunciators, displays and solid-state indicator lamps.


Full Wave Bridge Rectifier

This component uses four diodes to perform full-wave rectification of an input AC voltage. Two diodes conduct during each half cycle, giving a full-wave rectified output voltage. The top and bottom terminals can be used as the input terminals for the AC voltage. The left and right terminals can be used as the output DC terminals.

Model

A full-wave bridge rectifier consists of four diodes.

Terminals 1 and 2 are the input terminals, so the input AC source is connected across 1 and 2. Terminals 3 and 4 are the output terminals, so the load is connected across 3 and 4.

When the input cycle is positive, diodes D1 and D2 are forward-biased and D3 and D4 are reverse-biased. D1 and D2 thus conduct current in the direction shown. The voltage developed is identical to the positive half of the input sine wave minus the diode drops.

When the input cycle is negative, diodes D3 and D4 become forward-biased and conduct current in the direction shown. Hence, the current flows in the same direction for both the positive and the negative halves of the input wave. A full-wave rectified voltage appears across the load.


Shockley Diode

The Shockley diode is similar to a standard diode. However, the Shockley diode remains off (or in forward blocking region) even if it is forward- biased. The Shockley diode conducts current in one direction only when the forward voltage exceeds the forward breakover voltage, also called the switching voltage.

See also: Diode


Silicon Controlled Rectifier

An SCR is a unidirectional current control device similar to a Shockley diode. The difference is that the SCR has a third terminal capable of supporting a digital gate connection, which adds another means of controlling the current flow. The SCR switches on when either the forward bias voltage exceeds the forward-breakover voltage or a positive current pulse is applied to the gate terminal.

See also: Shockley Diode


Diac

A diac is a voltage dependent bidirectional switch. It functions like two parallel Shockley diodes aligned back-to-back. The diac restricts current flow in both directions until the voltage across the diac exceeds the switching voltage. When the voltage exceeds the switching voltage the diac conducts current in the direction of the voltage.

See also: Shockley Diode


Triac

A triac is a bi-directional switch capable of conducting current in both directions. It is composed of two parallel SCRs aligned back-to-back. The triac remains off restricting current in both directions until the voltage across the triac exceeds the breakover voltage, or until a positive pulse of current is applied to the gate terminal.

See also: SCR


Indicators Parts Bin

Voltmeter

Ammeter

Bulb

Probe

7-Segment Display

Decoded 7 Segment Display

Buzzer

Bargraph Display

Decoded Bargraph Display


Voltmeter

Use the voltmeter to measure DC or AC voltage differences between points in a circuit. Attach its probes in parallel with the points you want to measure. The side with the darker border is the negative terminal. You can use as many voltmeters as you want.

To specify whether the voltmeter is to measure the DC or AC component of a signal, double-click it and choose the mode you want. When set to AC, the voltmeter displays the RMS value of the signal.

The voltmeter is preset to a very high internal resistance (1MΩ), which generally has no effect on a circuit. You can increase this resistance; however, using an extremely high-resistance voltmeter in a low-resistance circuit may result in a mathematical error during simulation.

Tip: You can also use the multimeter as a voltmeter.


Ammeter

Insert an ammeter in series with the circuit wherever you want to measure current. The side with the darker border is the negative terminal. You can use as many ammeters from the parts bin as you want.

To specify whether you want an ammeter to measure a signal's DC or AC component, double-click it, then choose the mode you want. When set to AC, the ammeter displays the RMS value of the signal.

The ammeter's internal resistance is preset to 1 mΩ, which should have little effect on a circuit. You can lower this resistance; however, using an ammeter with very low resistance in a high-resistance circuit may result in a mathematical error during simulation.

Tip: You can also use the multimeter as an ammeter.


Bulb

The light bulb is a resistive component that dissipates energy in the form of light. Specify its power rating in watts (Pmax) from mΩ to kΩ, and its maximum voltage (Vmax) from mV to kV. The bulb will blow out if the voltage across it exceeds Vmax or the wattage across it exceeds Pmax.

In AC circuits, Vmax is the peak value of the voltage, not its RMS value.


Decoded Seven-Segment Display

The decoded seven-segment display is easier to use than the regular seven segment display, since it requires only four inputs. Each hexadecimal digit (0 to 9 and A to F) is displayed when its 4-bit binary equivalent is received.

See also: Seven-Segment Display


Seven-Segment Display

The seven-segment display actively shows its state while the circuit is running. The seven terminals control segments a to g.

        a

      -----

  f  |  g  |  b

       ---

  e  |     |  c

      -----

        d

When the value at a terminal is high (1), the corresponding segment lights up.

See also:  Decoded seven-segment display


Probe

The probe, corresponding to an LED (light-emitting diode), lights up when a "1" or high value reaches the input terminal. It requires no external resistor or ground connection, though practical circuits must supply them.

Attach the probe to any point in a digital circuit to monitor high and low levels. You can use the probe to show the action of counters and similar circuits.


Buzzer

The buzzer makes use of the computer's built-in speaker to simulate a piezoelectric buzzer.

It causes the computer's speaker to beep at a set frequency when the voltage across its terminals exceeds its set voltage.


Bargraph Display

The bargraph display is an array of 10 LEDs arranged side-by-side. This component may be used to indicate visually the rise and fall of a voltage. The voltage to be measured needs to be decoded into levels using comparators which are used to drive each individual LED. The terminals on the left side of the display are anodes and the terminals on the right are cathodes. Each LED lights up when the turn-on current, Ion flows through it.


Decoded Bargraph Display

The decoded bargraph display consists of 10 LEDs arranged side-by-side, just like the regular bargraph display. The difference is that the decoded bargraph display has decoding circuitry built-in so that the only input it requires is the voltage to be measured.

The circuitry inside decodes the voltage and lights up the appropriate number of LEDs depending on the voltage level.

The decoded bargraph display also offers a very high resistance to the input voltage. The voltage at which each LED lights up from lowest to highest is given by the formula:

    Von = V1 + (Vh - V1)/9 * (n - 1)

where

    n = 1, 2, ..., 9 (the number of LED)

    Vl = minimum voltage required for the lowest segment

         (default 1V)

    Vh = minimum voltage required for the highest segment

         (default 10V)

See also:  Bargraph Display


Instruments

Multimeter

Function Generator

Oscilloscope

Bode Plotter

Word Generator

Logic Analyzer

Logic Converter


Multimeter

Use the multimeter to measure AC or DC voltage or current, resistance or decibel loss between two points in a circuit. The multimeter is auto-ranging, so a measurement range does not need to be specified. Its internal resistance and current are preset to near-ideal values, which can be changed by clicking Settings.

For more information see:

Measurement Options

Signal Mode (AC or DC)

Internal Settings


Multimeter Measurement Options

A (Ammeter)

V (Voltmeter)

Ω (Ohmmeter)

dB (Decibels)


A (Ammeter) Multimeter Option

This option measures current through the circuit at the node.

The multimeter mustbe inserted in series with the load to measure current flow, just as with a regular ammeter. To measure current at another point in the circuit, the multimeter must be reconnected in series and the circuit must be activated again. When used as an ammeter, the multimeter's internal resistance is very low. It can be changed using the Settings button.

Note  To measure current at several points in a circuit, insert ammeters from the indicators parts bin.


V (Voltmeter) Multimeter Option

This option measures voltage between two points. Select V and attach the voltmeter's probes in parallel with (across from) the load.

After the circuit has been activated, the probes may be moved around to measure voltage between other points. When used as a voltmeter, the multimeter has a high internal resistance of 1 MΩ. It can be changed using the Settings button.

Note  To measure voltage at many points in a circuit, insert several voltmeters from the instruments parts bin.


W (Ohmmeter) Multimeter Option
Ω (Ohmmeter) Multimeter Option

This option measures resistance between two test points. The test points and everything that lies between them are called the "component network".

To get an accurate measurement, make sure that:

there is no source in the component network

the component or component network is grounded

the multimeter is set to DC

there is nothing else in parallel with the component or component network.

The ohmmeter generates a 1-mA current, which can be changed  using the Settings button. If the ohmmeter has been attached to different test points, re-activate the circuit to get a reading.


Db (Decibels) Multimeter Option

Measures decibel loss between two points in a circuit.

The Decibel standard for calculating dB is preset to 1 V, but can be changed using Settings.


Signal Mode (AC or DC) on Multimeter

The sine-wave button measures the root-mean-square (RMS) voltage or current of an AC signal. Any DC component of the signal will be eliminated, so only the AC component of the signal is measured.

The straight-wave button measures the current or voltage value of a DC signal.

Note  To measure the RMS voltage of a circuit with both AC and DC components, connect an AC voltmeter as well as a "DC" voltmeter across the appropriate nodes and measure the AC and DC voltage.  Use the following formula:

RMS voltage = (Vdc2 + Vac2)

This is not a universal formula. It is used in Electronics Workbench only.


Internal Settings of Multimeter

Ideal meters have no effect on the circuit being measured. An ideal voltmeter would have infinite resistance, so no current could flow through it while attached to a circuit. An ideal ammeter would present no resistance to a circuit. Real meters do not achieve this ideal, so their readings will not match theoretical, calculated values for a circuit.

The multimeter in Electronics Workbench, like a real multimeter, is nearly ideal. It uses very small and very large numbers that approximate zero and infinity to calculate near-ideal values for the circuit. For special cases, the meter's behavior can be changed by changing the value used to model its action. (The values must be higher than 0.)

For example, if testing the voltage of a circuit with very high resistance, increase the voltmeter's resistance. If measuring the current of a circuit with very low resistance, decrease the ammeter's resistance even further.

Note  Very low ammeter resistance in a high-resistance circuit may result in a mathematical roundoff error.

To display internal settings, click the Settings button.

Symbol	Multimeter Settings	Default 	Value Range

R	Ammeter resistance	1 Ω	 pΩ-Ω

R	Voltmeter resistance	1 GΩ	 Ω-TΩ

I	Ohmmeter current	0.01 μA	 μA-kA

V	Decibel standard	1 V	 μV-kV


Function Generator

The function generator is a voltage source that supplies sine, triangular or square waves. It provides a convenient and realistic way to supply power to a circuit. The waveform can be changed and its frequency, amplitude, duty cycle and DC offset can be controlled. The function generator's frequency range is great enough to produce conventional current as well as audio- and radio-frequency signals.

The function generator has three terminals through which waveforms can be applied to a circuit. The common terminal  provides a reference level for the signal.

To reference a signal from ground, connect the common terminal to the ground component.

The positive terminal (+) provides a waveform in the positive direction from the neutral common terminal. The negative terminal (-) provides a waveform in the negative direction.

For more information, see:

Waveform

Signal Options


Waveform (Function Generator)

To select the waveform, click the sine-, triangular- or square-wave  button.

To modify the triangular and square waveforms, change the duty cycle, as described in Signal Options.


Signal Options (Function Generator)

Frequency (1 Hz  999 MHz)

This options determines the number of cycles per second the function generator generates.

Duty Cycle (1%  99%)

This option sets the ratio of on-period to off-period. It affects the shape of triangular and square waves as shown below. A sine wave is not affected by the duty cycle setting.

Amplitude (1 V  999 kV)

This option controls the signal's voltage, measured from its DC level to its peak. If the leads are connected to the common and either the positive or the negative terminal, the wave's peak-to-peak measurement is twice its amplitude. If the output comes from the positive and negative terminals, the wave's peak-to-peak measurement is four times its amplitude.

Offset (-999 kV and 999 kV)

This option controls the DC level about which the alternating signal varies. An offset of 0 positions the waveform along the oscilloscope's x-axis (provided its Y POS setting is O). A positive value shifts the DC level upward, while a negative value shifts it downward. Offset uses the units set for Amplitude.


Oscilloscope

The dual-channel oscilloscope displays the magnitude and frequency variations of electronic signals. It can provide a graph of the strength of one or two signals over time, or allow comparison of one waveform to another.

Once a circuit has been activated and its behavior simulated, the oscilloscope's probes may be moved to other test points without re-activating the circuit. Moving the probes automatically redraws the waveforms for the new test points. The oscilloscope's settings can be fine-tuned either during or after simulation and the display will redraw automatically.

Tip  If the oscilloscope settings or analysis options are changed to provide more detail, the waveforms may appear choppy or uneven. If so, activate the circuit again to get more detail. You can also increase the precision of a waveform by increasing the simulation time step. (Choose the Instruments tab from the Analysis/Analysis Options dialog box.)

For more information, see:

Time Base (0.10 ns/Div-1s/Div)

Grounding

Channel A and Channel B Settings

Trigger

Enlarging the Oscilloscope (Expand)


Time Base (0.10) ns/Div-1s/Div) of Oscilloscope

The time base setting controls the scale of the oscilloscope's horizontal or x-axis when comparing magnitude against time (Y/T).

To get a readable display, adjust the time base in inverse proportion to the frequency setting on the function generator or AC sourcethe higher the frequency, the lower (or more magnified) the time base.

For example, if you want to see one cycle of a 1 kHz signal, the time base should be around 0.10 milliseconds. One cycle at 10 kHz requires a time base of about 0.01 milliseconds.

X Position (-5.00  5.00)

This setting controls the signal's starting point on the x-axis. When X Position is 0, the signal starts at the left edge of the display. A positive value shifts the starting point to the right. A negative value shifts the starting point to the left.

Axes (Y/T, A/B, B/A)

The axes of the oscilloscope display can be switched from showing waveform magnitude against time (Y/T) to showing one input channel against the other (A/B or B/A). The latter settings display frequency and phase shifts, known as Lissajous patterns, or they can display a hysteresis loop. When comparing channel A's input against channel B's (A/B), the scale of the x-axis is determined by the volts-per-division setting for channel B (and vice versa).

Tip  To analyze waveforms in detail, click "Pause after each screen" in the Instruments tab of the Circuit/Analysis Options dialog box or choose Analysis/Pause. In either case, continue the simulation when ready by choosing Analysis/Resume, or by pressing F9.


Grounding of Oscilloscope

It is not necessary to ground the oscilloscope, as long as the circuit to which it is attached is grounded.


Channel A and Channel B Settings of Oscilloscope

Volts per Division (0.01 mV/Div  5 kV/Div)

This setting determines the scale of the y-axis. It also controls the x-axis scale when A/B or B/A is selected.

To get a readable display, adjust the scale in relation to the channel's expected voltage. For example, an input AC signal of 3 volts fills the oscilloscope's display vertically when the y-axis is set to 1 V/Div. If the volts-per-division is increased, the waveform will become smaller. If the volts-per-division is decreased, the waveform's top will be cut off.

Y Position (-3.00  3.00)

This setting controls the point of origin for the y-axis. When Y position is set to 0.00, the point of origin is the intersection with the x-axis. Increasing Y position to 1.00, for example, moves 0 (the point of origin) up to the first division above the x-axis. Decreasing Y position to -1.00 moves 0 down to the first division below the x-axis.

Changing the Y position setting for channels A and B may help distinguish their waveforms for comparison. For the oscilloscope display illustrated below, the waveforms for channels A and B were almost superimposed. Because the Y position value was increased for channel A and decreased for channel B, the waveforms can now be clearly distinguished.

Input Coupling (AC, 0, DC)

With AC coupling, only the AC component of a signal is displayed.  AC coupling has the effect of placing a capacitor in series with the oscilloscope's probe. As on a real oscilloscope using AC coupling, the first cycle displayed is inaccurate. Once the signal's DC component has been calculated and eliminated during the first cycle, the waveforms will be accurate.

With DC coupling, the sum of the AC and DC components of the signal is displayed. Selecting 0 displays a reference flat line at the point of origin set by Y position.

Note  Do not place a coupling capacitor in series with an oscilloscope probe. The oscilloscope will not provide a path for current, and the analysis will consider the capacitor improperly connected. Instead, choose AC coupling.


Trigger of Oscilloscope

The trigger settings determine the conditions under which a waveform is first displayed on the oscilloscope.

Trigger Edge

To start displaying the waveform on its positive slope or rising signal, select the ascending edge button.

To start with the negative slope or falling signal, select the descending edge button.

Trigger Level (-300  3.00)

The trigger level is the point on the oscilloscope's y-axis that must be crossed by the waveform before it is displayed. The level can have any value between 3.00 (the top of the display) and -3.00 (the bottom of the display).

Tip  A flat waveform will not cross the trigger level. To see a flat signal, make sure the triggering signal is set to Auto.

Trigger Signal

Triggering can be internal, with reference to the input signal for channel A or B, or external, with reference to a signal through the external trigger terminal situated below the ground terminal on the oscilloscope icon. If a flat signal is expected, or if signals are to be displayed as soon as possible, select Auto.


Enlarging the Oscilloscope (Expand)

The Expand button expands the graphical display of the oscilloscope, moving the controls to the bottom of the window.

To display the exact values of the wave, drag the vertical cursor until the desired portion appears. The boxes below the display show the time and the voltage at the probe connections, where the vertical cursor intersects the sine wave, and the difference between the two positions.

To print the display of the expanded oscilloscope, choose File/Print and select XY Plot. The expanded oscilloscope must be displayed for this option to appear on the File/Print dialog box.


Bode Plotter

The Bode plotter produces a graph of a circuit's frequency response and is useful for analyzing filter circuits. The Bode plotter is used to measure a signal's voltage gain or phase shift. When the Bode plotter is attached to a circuit, a spectrum analysis is performed.

The Bode plotter generates a range of frequencies over a specified spectrum. The frequency of any AC sources in the circuit does not affect the Bode plotter. However, an AC source must be included somewhere in the circuit.

The initial and final values of the vertical and horizontal scales are preset to their maximum value. These values can be changed to see the plot on a different scale. If the scale is expanded or the base changed after simulation is complete, it may be necessary to activate the circuit again to get more detail in the plot. Unlike most test instruments, if the Bode plotter's probes are moved to different test points, it's best to re-activate the circuit to ensure accurate results.

For more information, see:

Magnitude or Phase

Vertical and Horizontal Axes Settings

Readouts


Magnitude or Phase of Bode Plotter

Magnitude of Bode plotter measures the ratio of magnitudes (voltage gain, in decibels) between two points, V+ and V-.

Phase measures the phase shift (in degrees) between two points.

Both gain and phase shift will be plotted against frequency (in hertz).

If V+ and V- are single points in a circuit:

1.	Attach the positive IN terminal and the positive OUT terminal to connectors at V+ and  V-.

2.	Attach the negative IN and OUT terminals to a ground component.

If V+ (or V-) is the magnitude or phase across a component, attach both IN terminals (or both OUT terminals) on either side of the component.


Vertical and Horizontal Axes Settings of Bode Plotter

Base Settings

A logarithmic base is used when the values being compared have a large range, as is generally the case when analyzing frequency response.

The base scale can be changed from logarithmic (LOG) to linear (LIN) without requiring that the circuit be activated again. (Only when using a logarithmic scale is the resulting graph considered a Bode plot.)

Horizontal Axis Scale (1.0 mHz  10.0 GHz)

The horizontal or x-axis always shows frequency. Its scale is determined by the initial (I) and final (F) settings for the horizontal axis. Since a frequency response analysis requires a large frequency range, a logarithmic scale is usually used.

Vertical Axis Scale

The units and scale for the vertical axis depend on what is being measured and the base being used, as shown in the table below.

Range and Units for Bode Plotter's Vertical Scale

When Measuring...	Using the Base...	Minimum Initial Value	Maximum Final Value

Magnitude (gain)	Logarithmic	-200 dB	200 dB

Magnitude (gain)	Linear	0	10e+09

Phase	Logarithmic	-720°	720°

Phase	Linear	-720°	720°

When measuring voltage gain, the vertical axis shows the ratio of the circuit's output voltage to its input voltage. For a logarithmic base, the units are decibels. For a linear base, the vertical axis shows the ratio of output voltage to input voltage. When measuring phase, the vertical axis always shows the phase angle in degrees. Regardless of the units, initial (I) and final (F) values for the axis can be set using the Bode plotter's controls.


Readouts of Bode Plotter

Move the Bode plotter's vertical cursor to get a readout of the frequency and magnitude or phase at any point on the plot. The vertical cursor is stored at the left edge of the Bode plotter display.

To move the vertical cursor:

click the arrows near the bottom of the Bode plotter, or

drag the vertical cursor from the left edge of the Bode plotter display to the point on the plot you want to measure.

The magnitude (or phase) and frequency at the intersection of the vertical cursor and the trace are shown in the boxes beside the arrows.


Word Generator

Use the word generator to send digital words or patterns of bits into circuits to test them.

For more information, see:

Entering Words

Creating, Saving and Reusing Word Patterns

Input Rate

Addressing

Triggering

Data Ready

Frequency


Entering Words in Word Generator

The left side of the word generator instrument face displays rows of 4-character hexadecimal numbers. Values of 4-character hexadecimal numbers range from 0000 to FFFF (0 to 65535, in decimal). Each horizontal row represents a binary 16-bit word. When the word generator is activated, a row of bits is sent in parallel to the corresponding terminals at the bottom of the instrument.

 To change a bit value in the word generator:

type the 16-bit number in the box labeled Binary (this will change the hexadecimal number in the scroll box), or

change the 4-character hexadecimal number in the scroll box (use the scroll bar, arrow keys, or PAGE UP and PAGE DOWN keys), or

type the equivalent ASCII characters in the box labeled  ASCII.

As the words are transmitted by the word generator, the value of each bit appears in the circles representing the output terminals at the bottom of the instrument.


Creating, Saving and Reusing Word Patterns in Word Generator

Click Pattern to display this dialog. With this dialog, you can save word patterns entered in the word generator to a file and load previously saved word patterns.  The dialog can also be used to generate useful patterns or to clear the display.


Input Rate of Word Generator

To inject the 16-bit words intoa circuit, click Step, Burst or Cycle. The current word appears in the box labeled Current.

To transmit one word at a time into the circuit, click Step.

To send all words in sequence, click Burst. Clicking Cycle sends a continuous stream of words that can be stopped by clicking Cycle again, or by pressing CTRL+T.

Use Breakpoint when you want to pause and restart the stream of words at a specified word.

To insert a breakpoint, select the word in the scroll window where you want the input to stop, then click Breakpoint.

To remove a breakpoint, click on an existing breakpoint in the scroll window, then click Breakpoint.

More than one breakpoint can be used. Breakpoints affect both Cycle and Burst.


Addressing in Word Generator

Each word in the word generator'sscroll window has an address, expressed as a 4-character hexadecimal number. When a word in the scroll box is changed, its address appears in the Edit box. As the word generator outputs words, each word's address appears in the Current box.

To create a subset of the words to be output, enter first and last addresses in the Initial and Final boxes.


Triggering Word Generator

Select Internal in the Trigger section on the word generator to have the internal clock of the word generator trigger the input cycle to the circuit. Select External if you wish to use an external signal to trigger the input cycle.

Use the edge buttons to control whether the input signal triggers the word generator on its ascending or descending edge.


Data Ready in Word Generator

This output pin lets the circuit know that data from the word generator is ready.


Frequency in Word Generator

Set the clock frequency of the word generator in Hz, KHz or MHz. Each word is placed on the output terminals for the duration of one clock cycle.


Logic Analyzer

The logic analyzer displays the levels of up to 16 digital signals in a circuit. It is used for fast data acquisition of logic states and advanced timing analysis to help design large systems and carry out troubleshooting.

The 16 terminals on the left side of the icon correspond to the terminals and horizontal rows across the instrument face.

When a circuit is activated, the logic analyzer records the input values on its terminals. When the triggering signal is seen, the logic analyzer displays the pre- and post-trigger data. Data is displayed as square waves over time. The top row displays values for channel 0 (generally the first bit in a digital word), the next row displays values for channel 1, and so on. The binary value of each bit in the current word is displayed in the terminals on the left side of the instrument face.

To specify the number of samples stored before and after triggering, choose the Instruments tab from the Analysis/Analysis Options dialog box.

The logic analyzer stores data until it reaches the pre-trigger number of samples. Then, it begins discarding samples as new samples appear until it sees the trigger signal. After the trigger signal, samples are stored up to the value of the post-trigger samples.

To change the threshold voltage, choose the Instruments tab from the Analysis/Analysis Options dialog box.

For more information, see:

Stop & Reset

Clock

Triggering


Stop & Reset in Logic Analyzer

To dump stored data when the logic analyzer is not triggered, click Stop. If the logic analyzer is already triggered and displaying data, Stop has no effect.

To clear the logic analyzer's display, click Reset.


Clock in Logic Analyzer

The clock informs the logic analyzer when to read an input sample. The clock can be internal or external.

To adjust the clock settings:

1.	Click Set in the Clock area of the logic analyzer. The Clock Setup dialog appears.

2.	Select positive or negative clock edge.

3.	Select external or internal clock mode.

4.	Click Accept.

Clock qualifier is an input signal that filters the clock signal. If it is set to x, then the qualifier is disabled and the clock signal determines when samples are read. If it is set to 1 or 0, the samples are read only when the clock signal matches the selected qualifier signal.


Triggering in Logic Analyzer

The logic analyzer can be made to trigger upon reading a specified word or combination of words.

To specify up to three trigger words or word combinations:

1.	Click Set in the Trigger box of the logic analyzer.

2.	Click in the box labeled A, B, or C and enter a binary word. An x means either 1 or 0.

3.	Click in the "Trigger combinations" box to select among eight combinations.

4.	Click Accept.

The eight trigger combinations are:

A

A OR B

A OR B OR C

A THEN B

(A OR B) THEN C

A THEN (B OR C)

A THEN B THEN C

A THEN (B WITHOUT C)

Trigger qualifier is an input signal that filters the triggering signal. If it is set to x, then the qualifier is disabled and the trigger signal determines when the logic analyzer is triggered. If it is set to 1 or 0, the logic analyzer is triggered only when the triggering signal matches the selected trigger qualifier.


Logic Converter

The logic converter is able to perform several transformations of a circuit representation. It has no real-world counterpart. It can be attached to a circuit to derive the truth table or Boolean expression the circuit embodies, or used to produce a circuit from a truth table or Boolean expression.

For more information, see:

Deriving a Truth Table from a Circuit

Entering and Converting a Truth Table

Entering and Converting a Boolean Expression


Deriving a Truth Table from a Circuit Using the Logic Converter

To derive a truth table from a circuit schematic:

1.	Attach the input terminals of the logic converter to up to eight input points in the circuit.

2.	Connect the single output of the circuit to the output terminal on the logic converter icon.

3.	Click the Circuit to Truth Table [image] button.

The truth table for the circuit appears in the logic converter's display.


Entering and Converting a Truth Table Using the Logic Converter

To construct a truth table:

1.	Click the number of input channels you want, from A to H, across the top of the logic converter.

The display area below the terminals fills up with the necessary combinations of ones and zeros to fulfill the input conditions. The values in the output column on the right are initially set to 0.

2.	Edit the output column to specify the desired output for each input condition.

To change an output value, select it and type a new value: 1, 0 or x. (An x indicates that either 1 or 0 is acceptable.)

To convert a truth table to a Boolean expression, click the Truth Table to Boolean Expression [image] button.

The Boolean expression will be displayed at the bottom of the logic converter.

To convert a truth table to a simplified Boolean expression, or to simplify an existing Boolean expression, click the Simplify [image] button.

The simplification is performed by the Quine-McCluskey method, rather than the more familiar Karnaugh mapping technique. Karnaugh mapping works for only small numbers of variables and requires human intuition, while Quine-McCluskey has proved to be exhaustive for any number of variables but is too cumbersome for manual solutions.

Note Simplifying a Boolean expression requires much memory. If not enough memory is available, Electronics Workbench may not be able to complete this operation.


Entering and Converting a Boolean Expression Using the Logic Converter

A Boolean expression can be entered in the box at the bottom of the logic converter using either sum-of-products or product-of-sums notation.

To convert a Boolean expression to a truth table, click the Boolean Expression to Truth Table [image] button.

To convert a Boolean expression to a circuit, click the Boolean Expression to Circuit [image] button.

The logic gates that fulfill the Boolean expression appear on the circuit window. The components are selected so you can move them to a different location on the circuit window or put them in a subcircuit. Deselect the components by clicking on an empty spot on the circuit window.

To see a circuit that fulfills the conditions of the Boolean expression using only NAND gates, click the Boolean Expression to NAND [image] button.


Logic Gates

2-Input AND Gate

2-Input OR Gate

NOT Gate

2-Input NOR Gate

2-Input NAND Gate

2-Input XOR Gate

2-Input XNOR Gate

Tristate Buffer

Buffer

Schmitt Trigger

AND Gates

OR Gates

NAND Gates

NOR Gates

NOT Gates

XOR Gates

XNOR Gates

Buffers


Buffer

The buffer is non-inverting. It has a greater fan-out and offers a high current source and sink capability for driving high current loads.

Buffer truth table:

  A  |  Y

-----------

  0  |  0

  1  |  1


Tristate Buffer

The tristate buffer is non-inverting with a three- state output. It has a greater fan-out and offers a high current source and sink capability for driving high current loads. The buffer has an active high enable input. If the device is not "enabled", then the buffer output goes into a high impedance (Z) state. In this state, the output pin is effectively disconnected from the rest of the circuit. Thus, the buffer is useful for circuits where outputs from different digital devices meet at the same node.

Tristate buffer truth table:

  A  | Enable |  Y

-------------------

  H  |   H    |  H

  L  |   H    |  L

  X  |   L    |  Z

where Z is a high-impedance state.


XNOR Gate

If an even number of inputs is high, the output is high. If an odd number of inputs is high, the output is low.

XNOR gate truth table:

  A  |  B  |  Y

-----------------

  0  |  0  |  1

  0  |  1  |  0

  1  |  0  |  0

  1  |  1  |  1


XOR Gate

If an odd number of inputs is high, the output is high. Otherwise, the output is low.

XOR gate truth table:

  A  |  B  |  Y

-----------------

  0  |  0  |  0

  0  |  1  |  1

  1  |  0  |  1

  1  |  1  |  0


NAND Gate

If one or more inputs is low, the output is high. If all inputs are high, the output is low.

NAND gate truth table:

  A  |  B  |  Y

-----------------

  0  |  0  |  1

  0  |  1  |  1

  1  |  0  |  1

  1  |  1  |  0


NAND Gate Theory

The NAND gate can be thought of as an AND gate, followed by a stage of inversion (a NOT gate is such an inverter). The NAND gate can also be created by inverting the two inputs of the OR gate. Either method results in the same truth table.

If NAND gate inputs are inverted, the truth table for the resulting logical function becomes that of the OR gate. The NOR gate with inverted inputs becomes an AND function. Logic circuits can be built with fewer chips using these techniques.


NOR Gate Theory

The NOR gate can be considered to be an OR gate, followed by a stage of inversion (the NOT gate is such an inversion stage). The NOR gate can also be created by inverting the inputs to the AND gate. Either method results in the same truth table.

If inputs to the NOR gate are inverted, the truth table becomes that of the AND gate. A NAND gate with inverted inputs becomes an OR gate. Logic circuits can be built with fewer chips using these techniques.


NOR Gate

If all inputs are low, the output is high. Otherwise the output is low.

NOR gate truth table:

  A  |  B  |  Y

-----------------

  0  |  0  |  1

  0  |  1  |  0

  1  |  0  |  0

  1  |  1  |  0


AND gate

If all inputs are high, the output is high. Otherwise, the output is low.

AND gate truth table:

  A  |  B  |  Y

-----------------

  0  |  0  |  0

  0  |  1  |  0

  1  |  0  |  0

  1  |  1  |  1


OR Gate

If one or more inputs is high, the output is high. If all inputs are low, the output is low.

OR gate truth table:

  A  |  B  |  Y

-----------------

  0  |  0  |  0

  0  |  1  |  1

  1  |  0  |  1

  1  |  1  |  1


AND Gates

The AND Gates component in the parts bin is a template. It has no pins or labels and cannot be wired into a circuit.

To use an IC (Integrated Circuit or chip), drag the template onto the circuit window. A list of available ICs for this family appears. Select the IC you want to include in your circuit. The correct graphic will appear containing labels and pins.

The AND Gates template includes:

4073 (3 3-Input AND)

4081 (4 2-Input AND)

7408 (4 2-Input AND)

7409 (4 2-Input AND)

7411 (3 3-Input AND)

7415 (3 3-Input AND)

7421 (2 4-Input AND)

7451 (AND-OR Inverter)

7454 (4-Wide AND-OR-Invert Gates)

7455 (2-Wide 4-Input AND-OR-INVERT Gates)


OR Gates

The OR Gates component in the parts bin is a template. It has no pins or labels and cannot be wired into a circuit.

To use an IC (Integrated Circuit or chip), drag the template onto the circuit window. A list of available ICs for this family appears. Select the IC you want to include in your circuit. The correct graphic will appear containing labels and pins.

The OR Gates template includes:

4071 (4 2-Input OR)

7432 (4 2-Input OR)

7451 (AND-OR Inverter)

7454 (4-Wide AND-OR-Invert Gates)

7455 (2-Wide 4-Input AND-OR-INVERT Gates)


NAND Gates

The NAND Gates component in the parts bin is a template. It has no pins or labels and cannot be wired into a circuit.

To use an IC (Integrated Circuit or chip), drag the template onto the circuit window. A list of available ICs for this family appears. Select the IC you want to include in your circuit. The correct graphic will appear containing labels and pins.

The NAND Gates template includes:

4011 (4 2-Input NAND)

4012 (2 4-Input NAND)

4023 (3 3-Input NAND)

4068 (8-Input NAND)

7400 (4 2-Input NAND)

7410 (3 3-Input NAND)

7412 (3 3-Input NAND)

7420 (2 4-Input NAND)

7422 (2 4-Input NAND)

7426 (4 2-Input NAND)

7430 (8-Input NAND)

7437 (4 2-Input NAND)

7438 (4 2-Input NAND)

7440 (2 4-Input NAND Buffers)

74133 (13-In NAND)


NOR Gates

The NOR Gates component in the parts bin is a template. It has no pins or labels and cannot be wired into a circuit.

To use an IC (Integrated Circuit or chip), drag the template onto the circuit window. A list of available ICs for this family appears. Select the IC you want to include in your circuit. The correct graphic will appear containing labels and pins.

The NOR Gates template includes:

4001 (4 2-Input NOR)

4002 (2 4-Input NOR)

4025 (3 3-Input NOR)

7402 (4 2-Input NOR)

7425 (2 4-Input NOR with Strobe)

7427 (3 3-Input NOR)

7428 (4 2-Input NOR)

7433 (4 2-Input NOR)


NOT Gates

The NOT Gates component in the parts bin is a template. It has no pins or labels and cannot be wired into a circuit.

To use an IC (Integrated Circuit or chip), drag the template onto the circuit window. A list of available ICs for this family appears. Select the IC you want to include in your circuit. The correct graphic will appear containing labels and pins.

The NOT Gates template includes:

4049 (Hex Inverting Buffers)

4069 (Hex inverter)

7404 (6 Inverter)

7405 (6 Inverter)

7406 (6 Inverter B/D)


XOR Gates

The XOR Gates component in the parts bin is a template. It has no pins or labels and cannot be wired into a circuit.

To use an IC (Integrated Circuit or chip), drag the template onto the circuit window. A list of available ICs for this family appears. Select the IC you want to include in your circuit. The correct graphic will appear containing labels and pins.

The XOR Gates template includes:

4030 (4 2-Input XOR)

4070 (4 2-Input XOR)

7406 (6 Inverter B/D)


XNOR Gates

The XNOR Gates component in the parts bin is a template. It has no pins or labels and cannot be wired into a circuit.

To use an IC (Integrated Circuit or chip), drag the template onto the circuit window. A list of available ICs for this family appears. Select the IC you want to include in your circuit. The correct graphic will appear containing labels and pins.

The XNOR Gates template includes:

74266 (4 2-Input XNOR)


Buffers

The Buffers component in the parts bin is a template. It has no pins or labels and cannot be wired into a circuit.

To use an IC (Integrated Circuit or chip), drag the template onto the circuit window. A list of available ICs for this family appears. Select the IC you want to include in your circuit. The correct graphic will appear containing labels and pins.

The Buffers template includes:

4049 (Hex Inverting Buffers)

4066 (4 Analog Switches)

7407 (6 Buffer B/D)

7440 (2 4-Input NAND Buffers)

74125 (4 Bus Buffer)

74126 (4 Bus Buffer)

74240 (Oct Buffer/Driver)

74241 (Oct Buffer/Driver)

74244 (Oct Buffer/Driver)

74365 (HEX Bus drivers with 3 State Outputs)

74367 (HEX Bus drivers with 3 State Outputs)

74368 (HEX Bus Drivers with 3 State Outputs)

74465 (Octal Buffers With 3 State Outputs)

74466 (Octal Buffers With 3 State Outputs)


7415 (3 3-Input AND)

AND gate truth table:

 A  B  C | Y

-------------

 1  1  1 | 1

 0  X  X | 0

 X  0  X | 0

 X  X  0 | 0


Schmitt Trigger

This component is basically a comparator with hysteresis. The internal comparator voltages are changed  each time the output changes state (high to low or low to high).

See also:

Hysteresis Block  (Controls parts bin)

The Schmitt trigger outputs:

0	if the voltage is rising and Vin > Vtg+

1	if the voltage is falling and Vin < Vtg-

where

Vtg+	= 1.6 V (Vih)

Vtg-	= 0.9 V (Vil)

Applications may be found in pulse and digital communications systems where noisy digital signals are frequently encountered and are required to be "cleaned up" into reliable digital signals without ambiguity.

In the example shown below, the Schmitt trigger is processing a noisy triangle waveform into a clean logic level pulse. The "noisy" waveform is produced by a 1.4v peak to peak sine wave superimposed on a clean triangular waveform representing the original signal before noise degradation.

When the input rises with less than 1,6V, the output is high. After the input crosses (becomes greater than) the 1.6V level for the first time, output changes to low and no further changes in output occur until the input crosses the 0.9V threshold in the negative direction. At this point, the output changes to high and the process repeats.

Non inverting Schmidtt triggers are also available from semiconductor manufacturers.


NOT Gate

If the input is high, the output is low. If the input is low, the output is high.

NOT gate truth table:

  A  |  Y

-----------

  0  |  1

  1  |  0

In addition to the obvious use this stage has for logic inversion, it is often used to construct more complex logic gates. For example, the AND gate followed by a NOT gate becomes the NAND gate. The OR followed by a NOT gate becomes a NOR gate.

Two NOT gates connected in series (one driving the other) become a non-inverting buffer stage, with high input impedance and low output impedance. In designing practical circuits, this can be useful for increasing the fanout (gate driving range) of a logic circuit, where circuit loading may be encountered.

See also:

AND Gates

OR Gates

NAND Gates

NOR Gates


Miscellaneous Parts Bin

Fuse

Write Data

SPICE Subcircuit (Netlist Component)

Lossy Transmission

Lossless Transmission

Crystal

DC Motor

Triode Vacuum

Boost Converter

Buck Converter

Buck-Boost Converter


Fuse

The fuse is a resistive component that protects against power surges and overloads in circuitry. If the current exceeds the specified maximum (Imx, in amps) the fuse will open ("blow") and cut off the current flow.

In AC circuits, Imx is the peak value of the current, not its RMS value.


Write Data

This component allows you to save simulation results as an ASCII file. It writes the time in seconds (simulation time, not real time) and the voltages at the nodes attached to its terminals. Terminals are numbered in the direction of the arrow on the components, and voltage data is numbered accordingly. Double-click the component to specify a filename.

The format of the data is:

Time <(space)> Voltage1 <(space)> Voltage2 ... <(space)> Voltage8

This is the same format as the PWL source component uses; therefore, you can use this component to generate input files for the PWL source component.

See also: PWL


SPICE Subcircuit

The SPICE subcircuit lets you insert subcircuits, such as a vendor's component model, into your circuit. You connect the SPICE subcircuit as you would any other component; however, the model used when you simulate is an external SPICE netlist.

Be aware that using the SPICE subcircuit is different from importing a circuit or subcircuit using File/Import. This generates a complete circuit schematic in the circuit window based on a SPICE netlist from an external file. The SPICE subcircuit, on the other hand, behaves as a subcircuit in your circuit. For more information on importing netlists, see Importing and Exporting Netlists.

To load a subcircuit:

1.	Double-click the SPICE subcircuit component. A file browser appears.

2.	Select the file containing the subcircuit.

3.	Click OK.

The SPICE subcircuit component supports all SPICE (SPICE3F5) components and SPICE netlist syntax. Commands are ignored.

The example shown below is a simple circuit that illustrates the CLC111buffer by Comlinear. The buffer netlist file is imported and simulated using the Netlist component. The netlist file's .CIR extension was renamed to a .LIB extension and stored in the C:\EWB5EDA \MODELS\SUBCKTS directory. The pin arrangements within the netlist file are applied to the terminals of the Netlist component in the order that they appear in the netlist file. You can view or modify the netlist file to see the relationship between the pins in the real life component and the pins it will correlate to in Electronics Workbench using any available text editor.


Lossy Transmission

The lossy transmission line is a 2-port network that represents a medium, for example, a wire or an interconnect, through which electrical signals pass.

The lossy model also models resistive losses in the line along with the characteristic impedance and propagation delay properties of the transmission line.

Note  The number of lumps has to be less than or equal to 128.  If you have more than one transmission line in the circuit, you may need to reduce the number of lumps in order to speed up the simulation.


Lossless Transmission

This component is a 2-port network that represents a medium, such as a wire or an interconnect, through which electrical signals pass.

The lossless model is an ideal one that simulates only the characteristic impedance and propagation delay properties of the transmission line. The characteristic impedance is resistive and is equal to the square-root of L/C.

Note  A lossy transmission line with zero loss can be used to model the lossless transmission line, and may be more accurate.


Crystal

This component is made of pure quartz and behaves as a quartz crystal resonator, a circular piece of quartz with electrodes plated on both sides mounted inside an evacuated enclosure. The piezoelectric characteristics of quartz give the crystal the characteristics of a very high Q tuned circuit. The piezoelectric effect of quartz crystal links the mechanical and electrical properties of the resonator. Electrode voltage causes mechanical movement. Likewise, mechanical displacement generates an electrode voltage.

An equivalent circuit for a crystal shows a large inductor in series with a small resistance and a capacitance. When mounted in a holder with connections, a shunt capacitance is added to the equivalent circuit. The resultant equivalent circuit means that the crystal has both a series and parallel resonant frequency very close together.

In the example circuit shown below, the impedance of the crystal is plotted by placing a 100k resistor in series. This is a rather crude method of impedance plotting but is useful in investigating basic concepts.

Series reasonance is represented by a low impedance and parallel resonance by a high impedance.

Note    The series resonance frequency (the sharp dip in the response curve) appears  slightly below the parallel resonant frequency (peak in the response curve). The sharpness of the peaks indicates a very high Q.


DC Motor

The component is a universal model of an ideal DC motor which can be used to model the behavior of a DC motor excited in parallel, in series or separately. The excitation type of the component is determined by the interconnection of the terminals between armature windings (terminals 1 and 2) and field windings (terminals 3 and 4).

To excite the DC motor in parallel, connect the positive terminal of a DC source to terminals 2 and 4; then connect the negative terminals of the DC source to terminals 1 and 3. To excite the DC motor in series, connect terminal 2 to terminal 3 (use a connector); then connect the positive terminal of a DC source to terminal 4 and connect the negative terminal of the DC source to terminal 1. To excite the DC motor separately, connect a DC source to terminals 2 and 1 (positive and negative, respectively); then connect another DC source to terminals 4 and 3 (positive and negative, respectively).

Terminal 5 is the DC motor's output. The output is the motor's rpm value. To display this value:

attach a voltmeter to terminal 5 (connect the other side of the voltmeter to ground) and simulate, or

attach the oscilloscope to terminal 5 and simulate (the rpm value is the voltage that appears), or

attach a connector to terminal 5, then choose an appropriate analysis from the Analysis menu (for example, if you choose Analysis/DC Operating Point, the rpm value is the voltage at the connector).

This component connects the electrical and mechanical parts of a servo-system. Input to the motor is electrical while output is mechanical.

The motor RPM (from a tachometer output) is proportional to voltage (1 RPM per volt).

Speed characteristics may be investigated by varying the field or armature supply  voltages. Speed may be varied by inserting a variable resistance in series with the field. This method only allows an increase of RPM as field current decreases.

Speed may also be varied by inserting a variable resistance in series with the armature. This method only allows for a decrease of RPM as resistance is increased.

In the example circuit shown below, the series resistance in both field and armature is minimum when the percentage indicates 0%. Field resistance is increased by pressing <shift>R and for the armature circuit by pressing <shift>A.


Triode Vacuum

This component behaves as a three-electrode tube consisting of an anode, cathode and plate electrode. It is often used as an amplifier in audio applications.

The vacuum tube is a voltage controlled current device, very similar in operation to an N channel FET.

As for an FET, the gain of the tube is referred to as transconductance and is defined as the change in plate current resulting from a change in grid to cathode voltage

gm =  (change in plate current)  / (change in grid to cathode voltage)

The example circuit (shown below) is a voltage amplifier.

With grid bias at -10V (grid -ve with respect to cathode), plate current is approximately  0.3mA. and voltage gain is approximately 10.

In a real situation, a bias battery or negative supply would not be used, for economic reasons.

As for an FET or transistor, self bias producing the same plate current and grid to cathode voltage is achieved by inserting a suitable value resistor in the cathode lead. A 27k resistor, bypassed with 10 microfarads, produces the same bias voltage and the same overall amplifier performance.

To test the self bias principle, move the bottom lead of Rg from the bias battery to ground and move the cathode lead from ground to the top of the R4/C3 self bias network.


Boost Converter

This component is an averaging circuit model that models the averaging behavior of a step-up DC-to-DC switching converter. It is based on a unified behavioral model topology. The topology models both small-signal and large-signal characteristics of this converter power stage. The model can be used to simulate DC, AC and large-signal transient responses of switched-mode power supplies operating in both the continuous and discontinuous inductor current conduction modes (CCM and DCM, respectively).

The boost converter is sometimes referred to as a Step Up Switchmode supply. Its basic application is to convert a low value, unregulated input voltage to a higher output voltage. For the model values used in this example, output voltage is determined by the relationship

Vo = V in/ (1-DC)

where DC is the switching duty cycle in the converter circuit.

The duty cycle (DC) is determined by the value of the control voltage (V2) and is proportional to V2 so the smaller the V2, the smaller the duty cycle and the lower the output voltage.

In the example shown below, the boost converter is stepping up a 5V input to 10V into a 50 ohm load when the control voltage is 0.5V (a duty cycle of 0.5 (50.%)). Adjusting the control voltage between 0.1V and 0.9V produces an output voltage between 5.5 and 48V.


Buck Converter

This component is an averaging circuit model that models the averaging behavior of a step-down DC-to-DC switching converter. It is based on a unified behavioral model topology. The topology models both small-signal and large-signal characteristics of this converter power stage. The model can be used to simulate DC, AC and large-signal transient responses of switched-mode power supplies, operating in both the continuous and discontinuous inductor current conduction modes (CCM and DCM, respectively).

The buck converter is sometimes referred to as a Step Down Switchmode supply. Its basic application is to convert a high value, unregulated input voltage to a lower output voltage. For the model values used in this example output voltage is determined by the relationship

Vo = V in*DC

where DC is the switching duty cycle in the converter circuit.

The switching duty cycle (DC) is determined  by the value of the control voltage (V2) and is proportional to V2 so that the smaller the V2, the smaller the duty cycle and the lower the output voltage.

In the example shown below, the boost converter is stepping a 12V input to 6V into a 50 ohm load when the control voltage is 0.5V ( a duty cycle of 0.5 (50.%)). Adjusting the control voltage between 0.1V and 0.9V produces an output voltage between 1.2V and 10.6V.

Note   Conversion efficiency may be calculated from (Vout*I out)/(Vin* I in).


Buck-Boost Converter

This component is an averaging circuit model that models the averaging behavior of a DC-to-DC switching converter. It is based on a unified behavioral model topology.  The topology models both small-signal and large-signal characteristics of this converter power stage.  This behavioral model can be used to simulate DC, AC and large-signal transient responses of a variety of switched-mode power supplies, operating in both the continuous and discontinuous inductor current condition modes (DCM and CCM, respectively).


Mixed ICs

ADC

DAC-I

DAC-V

Monostable

555 Timer


ADC

An ADC is a special type of encoder that converts the input analog voltage to an equivalent output digital word. There are five inputs and nine outputs.


DAC-I

The DAC is a generic current output digital-to-analog converter that converts a digital signal to an analog equivalent. It is a multiplying-type with both voltage output and current output. It converts an input binary 8-bit digital word to an equivalent analog voltage or current. There are 10 input pins and two output pins.  The DAC produces an output current that is proportional to the magnitude of the decimal equivalent of binary digital input. A second output, the complement of the first, is available at the second output pin.


DAC-V

The DAC-V is a voltage output DAC similar to the current output DAC.


Monostable

This component produces an output pulse of a fixed duration in response to an "edge" trigger at its input. The length of the output pulse is controlled by the timing RC circuit connected to the monostable multivibrator.

Model

A monostable multivibrator has two digital inputs: A1 and A2. The multivibrator can be triggered by a positive edge of digital signal at A1 or a negative edge at A2. Once triggered, it ignores further inputs.

An RC combination connected to RT/CT and CT pins controls the duration of the pulse produced by the monostable at Q. A complementary output is produced at W.

To operate the monostable, the following connections may be used:

Connect a series resistor (R) and capacitor (C) to the CT input.

Connect the junction of the R and C to the RT/CT.

Connect VCC  to a voltage source.

The output Y will give a pulse of duration 0.0693*R*C when either a positive clock edge is given to A1 or a negative edge is given to A2.

The threshold voltage (at which triggering starts) can be changed by modifying the model.


555 Timer

The 555 timer is an IC which is commonly used as an astable multivibrator, a monostable multivibrator or a voltage-controlled oscillator. The 555 timer consists basically of two comparators, a resistive voltage divider, a flip-flop and a discharge transistor. It is a two-state device whose output can be either a high voltage level or a low voltage level. The state of the output can be controlled by proper input signals and time-delay elements connected externally to the 555 timer.

See also:

Comparator

Flip-Flop

Transistor


Simulation Hints

Circuit Simulation Mechanism

Four Stages of Circuit Simulation

Equation Formulation

Equation Solution

Convergence Assistance Algorithms

About Convergence Problems and Simulation Failure

Transient Analysis Issues

DC Operating Point Analysis Issues

Solutions to DC Operating Point Analysis Failures

Solutions to Transient Analysis Failures


About Convergence Problems and Simulation Failure

For a variety of reasons, the simulator in Electronics Workbench is occasionally unable to complete a simulation or an analysis. The information in this section will help you understand typical causes of simulation or analysis problems, and will help you solve these problems.

Electronics Workbench uses the modified Newton-Raphson method to solve nonlinear circuits. When a circuit includes nonlinear components, multiple iterations of a set of linear equations are used to account for the nonlinearities. The simulator makes an initial guess at the node voltages, then calculates the branch currents based on the conductances in the circuit. The branch currents are then used to recalculate the node voltages and the cycle is repeated. This cycle continues until all of the node voltages and branch currents fall within user-defined tolerances, that is, convergence occurs. You can specify tolerances and iteration limits for the analysis in the Global, DC and Transient   tabs of the Analysis/Analysis Options dialog box.

If the voltages or currents do not converge within a specified number of iterations, an error message is produced and the simulation is aborted (typical messages include "Singular matrix," "Gmin stepping failed," "Source steppingfailed" and "Iteration limit reached").

Error messages contain syntax information such as shown in the following examples:

V1#branch

where V1 is the reference ID of a voltage source and branch is the current across V1

AR1[D1]

where AR1 is the reference ID of an opamp and D1 is the diode inside the model of AR1

R1:name

where R1 is the reference ID of a resistor and name  is the name of the subcircuit containing R1


Transient Analysis Issues

If transient analysis is being performed (time is being stepped) and the simulator cannot converge on a solution using the initial time step, the time step is automatically reduced, and the cycle is repeated. If the time step is reduced too far, an error message ("Timestep too small") is generated and the simulation is aborted.


DC Operating Point Analysis Issues

DC operating point analysis may fail to converge for various reasons. The initial guesses for the node voltages may be too far off, the circuit may be unstable or bistable (there may be more than one solution to the equations), there may be discontinuities in the models or the circuit may contain unrealistic impedances.

Note  All error messages generated during an analysis appear in the Error Log tab of the Analysis/Display Graphs dialog box.

Use the techniques in Solutions to DC Operating Point Analysis Failures  and Solutions to Transient Analysis Failures to solve many convergence problems and analysis failures. Before you proceed, identify which analysis is causing the problem (keep in mind that DC operating point analysis is often performed as the first step of other analyses). In each of the solutions, begin with step 1, then continue performing the subsequent steps, in order, until the problem is solved.


Solutions to DC Operating Point Analysis Failures

1.	Check the circuit topology and connectivity. Make sure that:

The circuit is correctly wired, and includes no dangling nodes or stray parts.

You haven't confused zeros with the letter O.

Your circuit has a ground node and every node in the circuit has a DC path to ground. Make sure no sections of your circuit are completely isolated from ground by transformers, capacitors, etc.

Capacitors and current sources are not in series.

Inductors and voltage sources are not in parallel.

All devices and sources are set to their proper values.

All dependent source gains are correct.

Your models/subcircuits have been correctly entered.

2.	Increase operating point analysis iteration limit to 200-300 in the  DC tab of the Analysis/Analysis Options dialog box. This allows the analysis to go through more iterations before giving up.

3.	Reduce the RSHUNT value by a factor of 100 in the Global tab of the Analysis/Analysis Options.

4.	Increase the Gmin minimum conductance by a factor of 10 in the Global tab of the Analysis/Analysis Options dialog box.

5.	Turn on "Use zero initial conditions" in the Analysis/Transient dialog box.


Solutions to Transient Analysis Failures

Transient analysis s performed as part of Parameter Sweep, Temperature Sweep, Worst Case andMonte Carlo analysis.

1.	Check the circuit topology and connectivity. See step 1 of Solutions to DC Operating Point Analysis Failures.

2.	Set relative error tolerance to 0.01 in the Global tab of the Analysis/Analysis Options dialog box. By increasing the tolerance from 0.001 (0.1% accuracy), fewer iterations are required to converge on a solution and the simulation finishes much more quickly.

3.	Increase transient time point iterations to 100 in the Transient  tab of the Analysis/Analysis Options dialog box. This allows the transient analysis to go through more iterations for each time step before giving up.

4.	Reduce the absolute current tolerance in the Global tab of the Analysis/Analysis Options dialog box if current levels allow. Your particular circuit may not require resolutions down to 1 μV or 1 pA. You should allow at least an order of magnitude below the lowest expected voltage or current levels of your circuit.

5.	Realistically model your circuit. Add realistic parasitics, especially junction capacitances. Use RC snubbers around diodes. Replace device models with subcircuits, especially for RF and power devices.

6.	If you have a controlled one-shot source in your circuit, increase its rise and fall times.

7.	Change the integration method to Gear in the Transient tab of the Analysis/Analysis Options dialog box. Gear integration requires longer simulation time, but is generally more stable than the trapezoid method.


Cicuit Simulation Mechanism
Circuit Simulation Mechanism

After you create a circuit schematic and turn on the power or click the simulate button, the solution of the circuit and generation of the data you see on instruments such as the oscilloscope is the role of the simulator. More specifically, the simulator is the part of Electronics Workbench that calculates a numerical solution to a mathematical representation of a circuit you created.

For this calculation to occur, each component in a circuit is represented by a mathematical model. Mathematical models link the schematic in the circuit window with the mathematical representation for simulation. The accuracy of the component models determines the degree to which simulation results match real-world circuit performance.

The mathematical representation of a circuit is a set of simultaneous, nonlinear differential equations. The main task of the simulator is to solve these equations numerically. A SPICE-based simulator transforms the nonlinear differential equations into a set of nonlinear algebraic equations. These equations are further linearized using the modified Newton-Raphson method. The resulting set of linear algebraic equations is efficiently solved using the sparse matrix processing LU factorization method.

For information on the stages of circuit simulation, see Four Stages of Circuit Simulation.

For an explanation of the formulating and solving methods used in the circuit simulation, see Equation Formulation  and Equation Solution.


Four Stages of Circuit Simulation

The simulator in Electronics Workbench, like other general-purpose simulators, has four main stages: input, setup, analysis and output.

At the input stage, after you have built a schematic, assigned values and chosen an analysis, the simulator reads information about your circuit.

At the setup stage,  the simulator constructs and checks a set of data structures that contain a complete description of your circuit.

At the analysis stage, the circuit analysis specified in the input stage is performed. This stage occupies most of CPU execution time and actually is the core of circuit simulation. The analysis stage formulates and solves circuit equations for the specified analyses and provides all the data for direct output or post-processing.

At the output stage, you view the simulation results. You can view results on instruments such as the oscilloscope, or on graphs that appear when you run an analysis from the Analysis menu or when you choose Analysis/Display Graphs.


Equation Formulation

In a circuit, each common point created by wires and connectors is called a node. The simulator calculates the voltage at each node. Each branch joining two nodes will have a separate current flowing through it.

To calculate a circuit solution, a circuit is represented internally as a system of equations, in the form:	A * X = B

where

A	= modified nodal admittance matrix with dimension n x n

X	= vector of unknowns with dimension n

B	= vector of constants, also with dimension n

n	= number of unknowns.

The system of equations is formulated using a general circuit analysis method called the Modified Nodal Approach (MNA).

The unknowns (n ) include each node voltage (excluding ground), as well as the voltage source currents. B contains the voltage and current source constants, and the entries in the admittance matrix (A ) are determined by Ohm's law and Kirchhoff's current and voltage laws.

The modified nodal admittance matrix is deemed sparse because it contains more zeros than non-zeros. Making use of a linked list, the solution of circuit equations can be performed by employing non-zero terms only. This method is called Sparse Matrix Technique. Generally, a sparse matrix approach requires less memory consumption and achieves faster simulation.


Equation Solution

Electronics Workbench solves circuit equations for linear and nonlinear circuits using a unified algorithm. The solution of a linear DC circuit is treated as a special case of general nonlinear DC circuits.

LU factorization is used to solve the system of sparse modified nodal matrix equations described previously (a set of simultaneous linear equations). This involves decomposing the matrix A into two triangular matrices (a lower triangular matrix, L, and an upper triangular matrix, U) and solving the two matrix equations using a forward substitution and a backward substitution.

Several efficient algorithms are used to avoid numerical difficulties due to the modified nodal formulation, to improve numerical calculation accuracy and to maximize the solution efficiency. These include:

A partial pivot algorithm that reduces the round-off error incurred by the LU factorization method.

A preordering algorithm that improves the matrix condition.

A reordering algorithm that minimizes nonzero terms for the equation solution.

A nonlinear circuit is solved by transforming it into a linearized equivalent circuit at each iteration and iteratively solving the linear circuit using the above-described method. Nonlinear circuits are transformed into linear ones by linearizing all nonlinear components in the circuit using the modified Newton-Raphson method.

A general nonlinear dynamic circuit is solved by transforming the circuit into a discretized equivalent nonlinear circuit at each time point and solving it using the method for a nonlinear DC circuit described above. A dynamic circuit is transformed into a DC circuit by discretizing all dynamic components in the circuit using an appropriate numerical integration rule.


Numerical Integration

To approximate the value of the integral of the differential equations used in the time-domain solution, Electronics Workbench optionally uses two numerical integration methods:

the Trapezoidal (default) method

the Gear (order from 1 to 6) method.

When the trapezoidal method is applied, the following approximation is used to discretize the differential equations:

where

Vn+1	= present unknown voltage value

Vn	= previous time-point solution

h	= time step length

n	= time interval.

The first-order Gear integration is the popular Backward Euler method. The second-order variable step size Gear integration formula is:

where

Vn+1	= present unknown solution

Vn	= previous first time-point solution

Vn-1	= previous second time-point solution

hn	= present time step

hn-1	= previous time step

You can change the maximum order for integration method using the Transient tab of the Analysis/Analysis Option dialog box. Using a higher order (3 through 6) Gear method theoretically leads to more accurate results, but slows down the simulation. Be aware that the maximum order for integration method is the maximum order that could be used, but that the simulator selects the most appropriate order based on the circuit.

Due to the nature of the nonlinear components, each time point may involve solving the admittance matrix several times before converging to a solution. The point solution is reached when the difference between consecutive voltage values is less than the tolerance calculated internally in terms of the absolute and relative tolerances specified in the Global tab  of the Analysis/Analysis Options dialog box.


Convergence Assistance Algorithms

Electronics Workbench uses two modified Newton-Raphson continuation algorithms, Gmin stepping and source stepping , to help find the solution during a DC operating point analysis of general nonlinear circuits.


Gmin Stepping

Gmin stepping is a multi-step iterative algorithm. The algorithm simply adds a conductance, Gmin, to the diagonal elements of the modified nodal admittance matrix so that a solution will converge more quickly. The basic concept is to keep the matrix well-conditioned.

Initially, a large Gmin value is applied and an approximate solution is found quickly. The initial value is set by the Gmin value times 10GminSteps Gmin. The Gmin value is taken from the "Gmin Minimum Conductance (GMIN)" on the Global tab of the Analysis/Analysis Options dialog box. The number of steps is set in "Steps in Gmin stepping algorithm" in the DC  tab of the Analysis/Analysis Options dialog box. The conductance is then reduced by a factor of ten and the circuit is solved again by setting the previous solution as the initial guess of the next iteration. When Gmin is reduced to zero, a final solution of the circuit is performed and the correct answer is obtained. This actually divides one single-step solution of the simple nonlinear iteration into a multi-step solution, which uses the same algorithm but has many smaller steps.


Source Stepping

The source stepping algorithm solves a nonlinear circuit problem by setting a fraction of the source vector as a parameter variable to aid the convergence of the DC solution. Similar to the Gmin stepping method, source stepping converts a single nonlinear circuit problem into a multi-step nonlinear circuit problem. Starting from a zero source vector, the source vector is slowly ramped up to its full DC value. At each source step, a simple nonlinear iteration solution is performed. The ramp rate is controlled by the number of steps set in "Steps in source stepping algorithm (SRCSTEPS)" on the DC tab of the Analysis/Analysis Options dialog box.


Sources Parts Bin

Ground

Battery

DC Current Source

AC Voltage Source

AC Current Source

Voltage-Controlled Voltage Source

Voltage-Controlled Current Source

Current Controlled Voltage Source

Current Controlled Current Source

Vcc Source

Vdd Source

Clock

AM Source

FM Source

Voltage-Controlled Sine Wave Oscillator

Voltage-Controlled Triangle Wave Oscillator

Voltage-Controlled Square Wave Oscillator

Controlled One-Shot

Piecewise Linear Source

Voltage-Controlled Piecewise Linear Source

Frequency-Shift-Keying Source (FSK Source)

Polynomial Source

Nonlinear Dependent Source


Ground

Ground is the reference point for relating electric voltage levels wherever electricity is used. The ground component provides this reference.

Not all circuits require grounding. Any circuit that uses an opamp, transformer, controlled source or oscilloscope must be grounded. Also, any circuit which contains both analog and digital components should be grounded. If such a circuit is ungrounded, you may see an error message or get invalid readings on instruments. It is important to ground both sides of a transformer or controlled source.


Battery

The battery is a DC voltage source. It can have any value from µV to kV.


DC Current Source

You can adjust the direct current source to any value from µA to kA.


AC Voltage Source

You can adjust the RMS value of the alternating voltage source to any voltage from µV to kV. You can also adjust its frequency and phase angle.


AC Current Source

You can adjust the RMS value of the alternating current source to any amperage from µA to kA. You can also adjust its frequency and phase angle.


Voltage Controlled Voltage Source
Voltage-Controlled Voltage Source

The magnitude of the voltage output of a voltage-controlled voltage source is dependent on the voltage applied at the input terminal. The two are related by a parameter called voltage gain (E), which is the ratio of the output voltage to the input voltage. Voltage gain can have any value from μV/V to kV/V.

See also: About Controlled Sources


Voltage Controlled Current Source
Voltage-Controlled Current Source

The magnitude of the current output of a voltage- controlled current source is dependent on the voltage applied at the input terminal. The two are related by a parameter called transconductance (G), which is the ratio of the output current to the input voltage. It is measured in mhos (also known as seimens) and can have any value from mmhos to kmhos.

See also: About Controlled Sources


Current Controlled Voltage Source

The magnitude of the voltage output of a current-controlled voltage source is dependent on the current through the input terminals. The two are related by a parameter called transresistance (H), which is the ratio of the output voltage to the input current. It can have any value from mΩ to kΩ.

See also: About Controlled Sources


Current Controlled Current Source

The magnitude of the current output of a current-controlled current source depends on the current through the input terminals. The two are related by a parameter called current gain (F), which is the ratio of the output current to the input current. The current gain can have any value from mA/A to kA/A.

See also: About Controlled Sources


Vcc Source

This is a quick and convenient source of a common supply voltage. The source is more compact than the battery symbol. It holds a point high, at +5 volts, corresponding to a binary "1" or logical TRUE.


Vdd Source

This is a quick and convenient source of a common supply voltage. The source is more compact than the battery symbol. It holds a point high, at +15 volts, corresponding to a binary "1" or logical TRUE.


Clock

The clock component is a square-wave generator. You can adjust its voltage amplitude, duty cycle and frequency.


AM Source

The single-frequency amplitude modulation source generates an amplitude-modulated wave. Use it to build and analyze communications circuits.


FM Source

The single-frequency frequency modulation source generates a frequency modulated wave. Use it to build and analyze communications circuits.


Voltage-Controlled Sine Wave Oscillator

This oscillator takes an input AC or DC voltage, which it uses as the independent variable in the piecewise linear curve described by the (control, frequency) pairs. From the curve, a frequency value is determined, and the oscillator outputs a sine wave at that frequency. When two co-ordinate pairs are used, the oscillator outputs a linear variation of the frequency with respect to the control input. When the number of co-ordinate pairs is greater than two, the output is piecewise linear. You can change the peak and valley values of the output sine wave.

Example

The example shows a sine wave generator with output frequency determined by a control voltage.

Control voltage may be DC, controlled by a potentiometer, as is the case for many signal generators and function generators, or may be the output from a PLL that determines a precise frequency.

The VCO (Voltage-Controlled Oscillator) is the "heart" of frequency synthesizers.

Control voltage may be a continuous variable of any desired shape as required in sweep generators and spectrum analysers.

In the example shown below, the VCO parameters are set so that control voltage of 0V produces an output frequency of 100Hz and a control voltage of 12V produces an output frequency of 20KHz.

The switch (activated by the S key) selects control voltages from a potentiometer or an AC sweep voltage from the function generator.

The potentiometer is activated by pressing F (increase frequency)  or SHIFT -F (decrease  frequency).

A square wave control voltage produces a form of FSK (frequency shift keying), a sine wave control voltage produces a form of FM (frequency modulation).


Voltage-Controlled Triangle Wave Oscillator

This oscillator is identical to the voltage-controlled sine wave oscillator except that it outputs a triangle wave. You can change the rise time duty cycle and the peak and valley values of the output triangle wave.

Example

The example shows a triangle wave generator with output frequency determined by a control voltage.

Control voltage may be DC, controlled by a potentiometer, as is the case for many signal generators and function generators.

Control voltage may be a continuous variable of any desired shape as required in sweep generators and spectrum analysers.

The VCO (Voltage-Controlled Oscillator) is the "heart" of frequency synthesizers.

In the example shown below, the VCO parameters are set so that control voltage of 0V produces an output frequency of 100Hz and control voltage of 12V produces an output frequency of 20KHz.

The switch (activated by pressing S) selects control voltages from a potentiometer or an AC sweep voltage from the function generator.

The potentiometer is activated by pressing F (increase frequency)  or SHIFT-F (decrease frequency).

A square wave control voltage produces a form of FSK (frequency shift keying), a sine wave control voltage produces a form of FM (frequency modulation).


Voltage-Controlled Square Wave Oscillator

This oscillator is identical to the voltage-controlled sine wave oscillator except that it outputs a square wave. You can change duty cycle, rise and fall times, and the peak and valley values of the output square wave.

Example: a square wave generator with output frequency determined by a control voltage.

Control voltage may be DC, controlled by a potentiometer, as is the case for many signal generators and function generators.

Control voltage may be a continuous variable of any desired shape as required in sweep generators and spectrum analysers.

The VCO (Voltage-Controlled Oscillator) is the "heart" of frequency synthesizers.

In the example shown below, the VCO parameters are set so that control voltage of 0V produces an output frequency of 100Hz and control voltage of 12V produces an output frequency of 20KHz.

The switch (activated by pressing S) selects control voltages from a potentiometer or an AC sweep voltage from the function generator.

The potentiometer is activated by pressing F (increase frequency) or SHIFT -F (decrease  frequency).

A square wave control voltage produces a form of FSK (frequency shift keying), a sine wave control voltage produces a form of FM (frequency modulation).


Controlled One-Shot

This component is an extremely versatile generator of pulse waveforms. The component takes an AC or DC input voltage, which it uses as the independent variable in the piecewise linear curve described by the (control, pulse width) pairs. From the curve, a pulse width value is determined, and the oscillator outputs a pulse of that width. You can change clock trigger value, output delay from trigger, output delay from pulse width, output rise and fall times, and output high and low values.

When two co-ordinate pairs are used, the oscillator outputs a linear variation of the pulse with respect to the control input. When the number of co-ordinate pairs is greater than two, the output is piecewise linear.

The output is triggered to a high state by any waveform which exceeds a preset trigger threshold at the CLOCK () input.

Output amplitude and rise and fall times may be set to match any application.

The pulse width is controlled by an input at the CONTROL VOLTAGE (+) input and may be DC or a varying waveform.

The potentiometer, activated by pressing R or SHIFT -R, supplies a variable DC control voltage to vary the output pulse width.

The CLEAR (C) input either resets the one shot or, if held at a high level, will inhibit triggering of the pulse output.

A varying control voltage waveform will produce Pulse Width Modulation (PWM).

A  voltage controlled triangle wave generator is included in the example circuit shown below. To observe the PWM effect, connect the triangle wave generator output in place of the potentiometer to the WIDTH ADJ terminal.


Piecewise Linear Source

This source allows you to control the shape of the waveform by entering time and voltage pairs of values. Each pair of values specifies the value of the source at the specified time. At intermediate values of time, the value of the source is determined by linear interpolation.

The component has two terminals and behaves as a voltage source when connected in a circuit. It reads a specified file which contains a table of time and voltage points. Using the data in the table, the component generates a voltage waveform specified by the input text file.

To use the PWL source:

1.	Drag PWL Source from the Sources toolbar to the circuit window.

2.	Double-click the component.

3.	Select the file containing the voltage and time points from the dialog box. (See "Input File Specification" below.)

Input Text File Specification

This file must contain a list of time and voltage points.  Each line of the file represents one point. The format is:

Time  <space(s)> Voltage

You can leave any amount of space between the Time  and Voltage  fields.  Here is an example of an ideally formatted input file:

0	0

2.88e-06	0.0181273

5.76e-06	0.0363142

1e-05	0.063185

1.848e-05	0.117198

If the PWL source encounters...	It will...

non-whitespace at beginning of line	ignore line

non-numeric data following correctly formatted data	accept data, ignore non-numeric data

non-whitespace between Time  and Voltage	ignore line

whitespace preceding correctly formatted data	accept data, ignore whitespace

Special Considerations

If the earliest input point is not at time 0.0, then the PWL source outputs the voltage of the earliest time point from time 0.0 to that earliest time.

After the latest input point, the PWL source outputs the voltage of the latest time point in the file from that latest time until the simulation ends.

Between input points, the PWL source uses linear interpolation to generate voltages.

The PWL source can handle unsorted data. It sorts the points by time before the simulation starts.

If you do not specify a filename, the PWL source behaves as a short circuit.

An easy way to generate an input file for the PWL source is to capture data using the Write Data component. If you capture more than one node voltage with Write Data and then use the resulting file for the PWL source, only the voltage waveform V1 will be used.

Example

The example waveform in the file DATA1.TXT consists of  two cycles of a square wave followed by a constant slope ramp to 0 volts, followed by a linear rise to 1.5V at 0.9sec and a linear fall to 0V at 1.2sec.

To produce this waveform, format of information in the data1.txt  file is as follows:

Point	Time	Voltage	Comment

1	0	0	starts at 0sec and 0V

2	0	1	at time 0, step to 1V, the rising edge.

3	.1	1	remain at 1V until 0.1 second

4	.1	0	fall to 0V at 0.1 sec, the falling edge

5	.2	0	stay at 0V  to 0.2 sec

6	.2	1	rising edge

7	.3	1	stay at 1V

etc.	The complete file may be viewed and modified using any 	text editor.


Voltage-Controlled Piecewise Linear Source

This source (voltage-controlled piecewise linear source) allows you to control the shape of the output waveform by entering up to five (input,output) pairs, which are shown in the Properties dialog box as (X,Y) co-ordinates.

The X values are input co-ordinate points and the associated Y values represent the outputs of those points. If you use only two pairs, the output voltage is linear.

Outside the bounds of the input co-ordinates, the PWL-controlled source extends the slope found between the lowest two co-ordinate pairs and the highest two co-ordinate pairs. A potential effect of this behavior is that it can unrealistically cause the output to reach a very large or very small value, especially for large input values. Therefore, keep in mind that this source does not inherently provide a limiting capability.

In order to reduce the potential for non-convergence of simulations, the PWL-controlled source provides for smoothing around the co-ordinate pairs. If input smoothing domain (ISD) is set to, say, 10%, the simulator assumes a smoothing radius about each co-ordinate point equal to 10% of the length of the smaller of the segments above and below each co-ordinate point.

Example

In the sample circuit shown below, a triangle waveform with uniform rise and fall slopes is modified to a parabolic waveform for which the slope increases at each reference point.

The co-ordinate pairs that perform this conversion are:

First pair 	0,0 	(no change)

Second pair 	1,1 	(same)

Third pair 	2,4 	(slope is increased between this pair and the last)

Fourth pair 	3,9 	(slope increased again)

Fifth 	4,16	(even steeper slope)

Note   In this example, the Y (output) is the square of the input. It is therefore an exponential.


Frequency-Shift-Keying Source (FSK)

FSK is used in digital communications systems such as in low speed modems (for example, a Bell 202 type modem - 1200 baud or less).

In this system, a digital high level is referred to as a MARK and is reproduced as a frequency of 1200 Hz. A digital low level is referred to as a SPACE and is represented by a frequency of 2200 Hz.

In the example shown below, the frequency shift keying signal is a 5v (TTL) square wave.

When the keying input is 5V, a MARK frequency of 1200 Hz is output. When keying voltage is 0V, a SPACE frequency of 2200 Hz is output.


Nonlinear Dependent Source

Use this source to create a single signal source modelling the  behaviour of a device or a complex system. This generic source allows you to create a sophisticated behavioral model by entering a mathematical expression. Expressions may contain the following operators:

+	-	*	/	^	unary-

and these predefined functions:

abs	asin	atanh	exp	sin	tan

acos	asinh	cos	ln	sinh	u

acosh	atan	cosh	log	sqrt	uramp

The functions u (unit step function) and uramp (integral of unit step) are useful in synthesizing piecewise nonlinear functions.

If the argument of log, ln or sqrt becomes less than zero, the absolute value of the argument is used. If a divisor becomes zero or the argument of log or ln becomes zero, an error will result.

The small-signal AC behavior of this source is a linear dependent source with a proportionality constant equal to the derivative of the source at the DC operating point.

Mathematical expression examples:

i	= cos(v(1)) + sin(v(2))

v 	= ln(cos(log(v(1,2))^2))) - v(3) ^ 4 + v(2) ^ v(1)

i 	= 17

To use the nonlinear dependent source:

1.	Double-click the component.

2.	Type the algebraic expression.

Note If the dependent variable is "V" the output is in volts; if the dependent variable is "I" the output is current.

AC and DC voltages and currents may be included in the modelling equation. In the example shown below, two DC voltage sources, an AC voltage source and an AC current source represent signals that are to be combined according to a mathematical function.

The equation is

Vo = V(1) + 2 V(2) + V(3) + (I(6)*1000).

For the input values and equation shown the output consists of a DC component of 7V and an AC component of 4V.


Polynomial Source

The polynomial source is a voltage-controlled voltage source defined by a polynomial transfer function. Use it for analog behavioral modeling. In Electronics Workbench, the polynomial source has three controlling voltage inputs, namely, V1, V2 and V3.


Grounding

A voltage measurement is always referenced to some point, since a voltage is actually a "potential difference" between two points in a circuit.

The concept of "ground" is a way of defining a point common to all voltages. It represents 0 volts. All voltage levels around the circuit are positive or negative when compared to ground. In power systems, the planet Earth itself is used for this reference point (most home power circuits are ultimately "grounded" to the Earth's surface for lightning protection). This is how the expression "earthing" or "grounding" a circuit originated.

Most modern power supplies have "floating" positive and negative outputs, and either output point can be defined as ground. These types of supplies can be used as positive (with respect to ground) or negative power supplies. In floating power supply circuits, the positive output is often used as the voltage reference for all parts of the circuit.


Voltage Sources

A voltage source is a power or signal source where the chief concern is the output voltage.

A DC voltage source or battery must supply voltage with good "regulation," meaning freedom from voltage drops caused by changes in load or line, and freedom from noise and AC ripple in the voltage output.

An AC voltage source, as a power source or as a signal generator, must provide a waveform free of distortion--the waveform must contain only the fundamental frequency of the AC generator with no multiple frequencies, called "harmonics."

If a voltage source is used as a variable frequency signal generator, its output impedance must remain constant as the frequency varies in order to avoid a varying output voltage. In many voltage signal sources it is also important that the output frequency remain highly stable.

A voltage source is often used in the analysis of electric networks, if the emphasis is on voltages appearing across components, rather than on current flowing into and out of points in the circuit.


Battery Background Information

A battery may be a single electrochemical cell or a number of electrochemical cells wired in series. It is used to provide a direct source of voltage and/or current.

A single cell has a voltage of approximately 1.5 volts, depending on its construction. It consists of a container of acid in which an electrode is placed. Chemical action causes electrons to flow between the electrode and the container, and this creates a potential difference between the electrode and the material of the container.

Batteries can be rechargeable and can be built to deliver extremely high currents for long periods. The automobile ignition battery is an application of a battery as a "current source"; the voltage may vary considerably under use, with no visible battery deterioration.

Batteries may be used as voltage references, their voltage remaining stable and predictable to many figures of accuracy for many years. The standard cell is such an application. A standard cell is a voltage source, and it is important that current is not drawn from the standard cell.


Controlled Sources

Electronics Workbench provides ideal sources in which the magnitude of the output depends on the voltage or current at the input.

There are four controlled sources:

Voltage-Controlled Voltage Source

Voltage-Controlled Current Source

Current-Controlled Voltage Source

Current-Controlled Current Source


Transistors Parts Bin

NPN Transistor

PNP Transistor

N-Channel JFET

P-Channel JFET

3-Terminal Depletion N-MOSFET

3-Terminal Depletion P-MOSFET

4-Terminal Depletion N-MOSFET

4-Terminal Depletion P-MOSFET

3-Terminal Enhanced N-MOSFET

3-Terminal Enhanced P-MOSFET

4-Terminal Enhanced N-MOSFET

4-Terminal Enhanced P-MOSFET

N-Channel GASFET

P-Channel GASFET


NPN BJT (Bipolar junction transistor)

The NPN BJT has two n-regions (collector and emitter) separated by a p-region (base). The terminal with the arrowhead is the emitter. The ideal NPN in the parts bin has generic values suitable for most circuits. You can specify a real-world transistor by double-clicking the icon and choosing another model.


PNP BJT (Bipolar junction transistor)

The PNP BJT has two p-regions (collector and emitter) separated by an n-region (base). The terminal with the arrowhead represents the emitter. The ideal PNP model has generic values suitable for most circuits. You can specify a real-world transistor by double-clicking the icon and choosing another model.


N-Channel JFET

This is an n-channel JFET (junction field-effect transistor). It is always operated with the gate-source pn junction reverse biased. The arrowhead terminal is the gate.

The more negative the gate-source voltage, the narrower the channel becomes, due to the effect of depletion layers. When the gate-source voltage reaches a value of Vgs(off), the depletion layers touch, cutting off the drain current.

An ideal n-channel JFET is included in the parts bin. You can specify another model to suit your needs.


P-Channel JFET

This is a p-channel JFET (junction field-effect transistor). Its operation is identical to that of an n-channel JFET, except that the gate-source must be positively biased. The arrowhead terminal is the gate.

An ideal p-channel JFET is included in the parts bin. You can specify another model to suit your needs.

See also: N-Channel JFET


3-Terminal Depletion N-MOSFET

This is an n-channel depletion MOSFET. Its substrate is connected to its source lead, making it a three-terminal device.


3-Terminal Depletion P-MOSFET

This is an p-channel depletion MOSFET. Its substrate is connected to its source lead, making it a three-terminal device.


3-Terminal Enhanced N-MOSFET

This is an n-channel enhancement MOSFET. Its substrate is connected to its source lead, making it a three-terminal device.


3-Terminal Enhanced P-MOSFET

This is a p-channel enhancement MOSFET. Its substrate is connected to its source lead, making it a three-terminal device.


4-Terminal Depletion P-MOSFET

This is a 4-terminal p-channel depletion MOSFET, with the substrate lead left unconnected.


4-Terminal Depletion N-MOSFET

This n-channel depletion MOSFET has four terminals instead of three because the substrate lead is not connected to the source lead.


4-Terminal Enhanced P-MOSFET

This is a p-channel enhancement MOSFET. Because the substrate and source leads are not connected, it has four terminals.


4-Terminal Enhanced N-MOSFET

This is an n-channel enhancement MOSFET. Because the substrate lead is not connected to the source lead, it has four terminals.


BJTs: Background Information

BJTs are operated in three different modes, depending on which element is common to input and output: common base, common emitter or common collector. The three modes have different input and output impedances and different current gains, offering individual advantages to a designer.

A transistor can be operated in its nonlinear region as a current/voltage amplifier or as an electronic switch in cutoff and saturation modes. In its linear region, it must be biased appropriately (i.e., subjected to external voltages to produce a desired collector current) to establish a proper DC operating point.

The transistors' parameters are based on the Gummel-Poon transistor model.


DC Operating Point

The DC operating point, also known as the Q or quiescent point, is the point at which the voltage and current of the source are the same as the voltage across, and the current into, the load. In other words, the output voltage is ideally a linear reproduction of the input.


 MOSFETs (Metal-Oxide-Semiconductor FETs)

Eight types of MOSFETs (metal-oxide-semiconductor field-effect transistors) are supplied in the parts bin. There are several models for each.

The MOSFET substrate is usually connected to its most negatively biased part, usually the source lead. In 3-terminal MOSFETs, the substrate is internally connected to the source. An n-channel MOSFET has an inward-pointing substrate arrow. A p-channel MOSFET has an outward-pointing arrow.

N-channel and p-channel MOSFETs are identical except their voltage polarities are reversed.

There are two main categories of MOSFETs:

Depletion MOSFETs

Enhancement MOSFETs

In the parts bin you'll find the following MOSFETs:

3-terminal depletion N-MOSFET

3-terminal enhanced N-MOSFET

3-terminal depletion P-MOSFET

3-terminal enhanced P-MOSFET

4-terminal depletion N-MOSFET

4-terminal enhanced N-MOSFET

4-terminal depletion P-MOSFET

4-terminal enhanced P-MOSFET


Enhancement MOSFETs

An enhancement MOSFET has no physical channel between the drain and the source, unlike the depletion MOSFET. Instead, the substrate extends all the way to the silicon dioxide (SiO2) layer.

An enhancement MOSFET works only with positive gate- source voltages. A positive gate-source voltage above a minimum threshold value (Vto) creates an inversion layer of charges in the substrate region adjacent to the SiO2 layer. The conductivity of this induced channel is enhanced by increasing the gate-source voltage on the positive side.

Enhancement MOSFETS are extensively used in digital circuits and large-scale integration (LSI) applications.

See also: Depletion MOSFETs


Depletion MOSFETs

Like a JFET, a depletion MOSFET consists of a length of p-type (for a p-channel MOSFET) or n-type (for an n-channel MOSFET) semiconductor material called the channel, which is formed on a substrate of the opposite type. This substrate reduces the channel between the drain and the source. Free electrons from the source to the drain have to pass through this narrow channel. The two ends of the channel are called the source and the drain.

The metal gate of the MOSFET is insulated from the channel by a thin layer of silicon dioxide (SiO2), so negligible gate current flows during operation. The more negative the gate-source voltage is in an n-channel MOSFET, the more the gate depletes the channel of its conduction electrons, thus reducing the drain current. At Vgs(off), the channel is totally depleted and the drain-to-source current is cut off. Alternatively, the more positive the voltage, the bigger the channel size, thus increasing the current flow. A p-channel MOSFET is identical to an n-channel MOSFET, except its voltage polarities are opposite.

Depletion MOSFETs are used in automatic-gain control (AGC) circuits.

See also:

Enhancement MOSFETs

JFET


JFETs (Junction Field-Effect Transistors)

A JFET (junction field-effect transistor) is a unipolar, voltage-controlled transistor that uses an induced electrical field to control current. The current through the JFET is controlled by its gate voltage. The more negative the voltage, the smaller the current.

A JFET consists of a length of n-type or p-type doped semiconductor material called a channel. The ends of the channel are called the source and the drain. In an n-channel JFET, the gate is p-type material surrounding the channel. In a p-channel device it is n-type material.

The parts bin includes two types of JFET:

N-channel JFET

P-channel JFET


 BJTs (Bipolar Junction Transistors)

BJTs (bipolar junction transistors) are current-based valves used for controlling electronic currents and for amplification and switching applications. They are three-layer devices with two junctions: base-emitter and base-collector.

BJTs come in two versions, PNP and NPN. They have different power supply polarities and internal current flow directions. The letters refer to the polarities (positive or negative) of the materials that make up the transistor "sandwich."

Transistors began the solid-state phase of electronics, and they still play an important part. Their small size made "chip" technology possible; even small ICs (integrated circuits) may contain many transistors. Transistors make battery power practical for instruments and communicators, allowing very complex systems to be light and portable.

The parts bin includes two BJTs:

NPN BJT

PNP BJT


N-Channel GASFET

This component is a high-speed field-effect transistor that uses gallium arsenide (GaAs) as the semiconductor material rather than silicon. A GaAsFET consists of a length of n-type or p-type doped GaAs called the channel. The ends of the channel are called the source and the drain. The terminal with the arrowhead represents the gate. GaAsFETs are used in microwave applications.


P-Channel GASFET

This component is a high-speed field-effect transistor that uses gallium arsenide (GaAs) as the semiconductor material rather than silicon. It is generally used as a very high frequency amplifier (into the gigahertz range). A GaAsFET consists of a length of n-type or p-type doped GaAs called the channel. The ends of the channel are called the source and the drain. The terminal with the arrowhead represents the gate. GaAsFETs are used in microwave applications.

In the example circuit shown below, the P channel GaAsFET is self biased by R2, bypassed for RF with C2.

If you use the Bode Plotter to analyse amplifier performance, you will see a gain of approximately 47dB at a resonant frequency of 918 MHz.

Since the ideal model for the GaAsFET is used in this example, there are no device capacitances included and the resonant frequency is very close to that calculated using L 1 and C3 alone.


Release Notes Contents

New in Version 5.0c

Notes About Instruments

Notes About Simulation

Notes About Components

Notes About Files

Parts Bin Options in Show/Hide Tab of Schematic Options Dialog Box

Revisions to Version 5 Documentation

For Version 4 Users


New in Version 5.0c

Components

IGBTs and Voltage Regulators (CA3085 and LM117) have been added under the SPICE Netlist component.

MOSFET models have been corrected.

Analysis

The speed of digital and mixed-mode simulation has been increased. It is now about twice as fast.

Instruments

External triggering works for the word generator and logic analyzer.

Circuits need a ground node and resistor attached to the instruments as a reference. A warning appears to notify you that this is required.

Miscellaneous

You can now load circuits from the command line.

The circuit window can be resized, and its new size gets saved with the circuit.

A number of examples have been added to the online help for the more complex components, to further clarify how these components work.

Importing and Exporting Circuits

Electronics Workbench will import and export node identification of circuits only if the identification is numeric. If a circuit being imported has anything other than a numeric node identifier, Electronics Workbench will rename the node and provide you with information about the renaming in a dialog box.


Notes about Instruments

The word generator is limited to 1024 words, not 64K.

The function generator is not available as a source for analysis.

Adjustments made to the function generator during the simulation are not recognized. You must stop and re-start simulation to make adjustments take effect.

The ohmmeter will not give a correct reading unless you ground the circuit.

The logic analyzer has undergone a number of changes.

Related Topics

Word Generator

Function Generator

Ohmmeter

Logic Analyzer

Changes to Logic Analyzer


Notes About Simulation

"Initial conditions" in the Node tab of the Circuit/Connector Properties dialog box refers to the initial voltage conditions of the node. The initial voltage condition is the voltage which the node is assumed to have at the beginning of the simulation.

As a default, all nodes have an initial voltage of zero volts unless modified.

Note: You cannot modify the initial conditions of a component.

Subcircuits are treated as a unit. As a result, you cannot directly access nodes that are in subcircuits. Also, components and nodes within subcircuits cannot be specified individually for analyses.

For smoother curves in Analysis Graphs, decrease the transient analysis setting (TMAX). Note that this will increase simulation time.

To use the analysis functions of Electronics Workbench, you must have at least one analog component in the circuit.

All SPICE components will work with any analysis. However, not all components work with all analyses. Below is a description of the type of components that will/will not work with specific analyses.

Not all analyses work with all components. If you have an XSPICE Component in your circuit, only the following analyses are available:

DC Operating Point

AC Frequency

Transient

Fourier

Parameter Sweep

Temperature Sweep

Monte Carlo

Not all analyses can be performed on all types of nodes. If you wish to do an analysis on a digital node (that is, a node that connects only digital components), you are restricted to the following ananlyses:

DC Operating Point

AC Frequency

Transient

Fourier

Parameter Sweep

Temperature Sweep

Monte Carlo

Only components with a Temperature Instance parameter can have their temperature modified. Click for list of components with temperature instance.


Notes About Components

The relay (Basic parts bin) now has an additional parameter, coil resistance.

When using opamps (Analog ICs parts bin), keep in mind the following:

TMAX is very important to accurate simulation, especially for netlist opamps from manufacturers.

The 3-terminal opamp is a behavioral model for system-level simulation. For a more accurate model, use the manufacturer's model from the 5-terminal list.

Netlists cannot be edited directly in Electronics Workbench. The edit button on the Models dialog box is not available if the selected component is a netlist. If necessary, use a text editor to edit the netlist.

The comparator (Analog ICs parts bin) is a 3-terminal one. If you want to use a 5-terminal comparator, use SPICE Subcircuit (Netlist Component) in the Miscellaneous parts bin to implement it.

The Vcc source (Sources parts bin) has been replaced with +Vcc (5V) and +Vdd (15V).

To use the SPICE Subcircuit (Netlist component) in the Miscellaneous parts bin, put your file(s) in the MODELS\SUBCKTS subdirectory of the directory where Electronics Workbench is installed. Note that all files must have an extension of .lib.

Reference IDs must be alphanumeric (0-9, a-z, A-Z, _).

A SPICE Subcircuit (Netlist component) cannot include nested subcircuits.

Related Topics

Relay

Opamps

Comparator

Vcc source

SPICE Subcircuit


SPICE Components

3 - Terminal Depletion N-MOSFET

3 - Terminal Depletion P- MOSFET

3 - Terminal Enhancement N- MOSFET

3 - Terminal Enhancement P- MOSFET

4 - Terminal Depletion N- MOSFET

4 - Terminal Depletion P- MOSFET

4 - Terminal Enhancement N- MOSFET

4 - Terminal Enhancement P- MOSFET

AC Current Source

AC Voltage Source

Ammeter

Battery

Boost Converter

Buck Converter

Buck-Boost Converter

Capacitor

Current-Controlled Current Source

Current-Controlled Voltage Source

Current-Controlled Switch

DC Current Source

Diode

FM Source

Full-Wave Bridge Rectifier

Inductor

LED

Lossless Transmission Line

Lossy Transmission Line

N-Channel GaAsFet

N-Channel JFET

NPN Transistor

P-Channel GaASFet

P-Channel JFET

PNP Transistor

Polarized Capacitor

Resistor

Switch

Variable Capacitor

Variable Inductor

Voltage-Controlled Voltage Source

Voltage-Controlled Current Source

Voltage-Controlled Switch

Voltmeter


XSPICE Components

Controlled-Oneshot

Coreless Coil

Current-Controller Limiter Block

Differentiator

Divider

Gain Block

Integrator

Magnetic Core

Multiplier

Summer

Transfer Function Block

Voltage-Controlled Analog Switch

Voltage-Controlled Sine Wave Oscillator

Voltage-Controlled Limiter

Voltage-Controlled Piecewise Linear Source

Voltage-Controlled Square Wave Oscillator

Voltage-Controlled Triangle Wave Oscillator

Voltage Hysteresis Block

Voltage Limiter

Voltage Slew Rate Block

Zener Diode


List of Components with Temperature Instance

3 - Terminal Depletion N-MOSFET

3 - Terminal Depletion P- MOSFET

3 - Terminal Enhancement N- MOSFET

3 - Terminal Enhancement P- MOSFET

4 - Terminal Depletion N- MOSFET

4 - Terminal Depletion P- MOSFET

4 - Terminal Enhancement N- MOSFET

4 - Terminal Enhancement P- MOSFET

Diode

LED

N-Channel JFET

NPN Transistor

P-Channel JFET

PNP Transistor


For Version 4 Users

Version 5 of Electronics Workbench uses different convergence criteria than Version 4 did. In general, Version 5 uses much tighter convergence criteria to guarantee accurate simulation. In Version 5, three error tolerance quantities (relative tolerance RELTOL, absolute current tolerance ABSTOL and absolute voltage tolerance VNTOL) are combined together as the convergence criteria. In Electronics Workbench Version 4, only one error tolerance (relative tolerance RELTOL) is used to control convergence. As a result, even if you use the same value for RELTOL, the actual error tolerance used to control the convergence will be different in Version 5.

Version 5 uses more accurate semiconductor device models than Version 4 did. Because these device models model more nonlinear effects of the semiconductor devices, they could cause more numerical problems than a simpler device model. This is particularly true when you simulate a circuit that employs both detailed semiconductor device models and simple ideal switch models.

Because Version 5 uses different semiconductor devices models, the model parameter values of a specific device (for example, Q2n2222) in Version 4 may no longer be valid or appropriate in Version 5. Using the same model parameter values in Version 5 may result in different results or convergence problems.


Parts Bin Options in Show/Hide Tab of Schematic Options Dialog Box

AutoHide Parts Bins - Selecting this option causes parts bins to close once you drag a component from them. De-selecting this option causes parts bins to stay open until you close them.

Keep Parts Bin Positions - Selecting this option causes parts bins, when re-opened, to appear in the location from which they were last closed. De-selecting this option causes parts bins to re-open in their default location.


Notes About Files

For users of Windows 95 or Windows NT, Electronics Workbench does not support long file names.

Before software files can be moved from one directory/folder to another, Electronics Workbench must be uninstalled from its current location. It can then by reinstalled, using the original install disks, in the new location.

Circuit files should not be edited using a text editor.


Technical Support

Have a Question?

There are a number of resources you have access to when trying to get answers to questions about Electronics Workbench:

Frequently Asked Questions (FAQs) can be reviewed on CompuServe, BBS and our Web page.

Documentation provided with Electronics Workbench should provide you with the information you need to perform any functions available.

On-line help is available while running Electronics Workbench.

If all else fails, contact our Technical Support Department.

How to Get Product Support

If you can't find a solution to your problem yourself, there are two basic ways to get in touch with us to enlist our aid: by phone or in writing. Writing down your problem offers many different delivery options, and means we can work on a solution while you're working on something else. Remember: Electronics Workbench  support is free and unlimited. And we promise a response to your question usually within one business day, whatever method you use to communicate with us.

Before You Call, Please:

Have your serial number ready from the back of the User's Guide, as well as the exact version of the software you are using.

If you use Windows, have your AUTOEXEC.BAT and CONFIG.SYS files available.

Be sitting at your computer with Electronics Workbench running.

How to Reach Us

If you have Internet access, send an e-mail message to support @ interactiv.com

Fax information to (416) 977-1818.

Log onto our BBS at (416) 977-3540 and send us a message.

From CompuServe, type GO EWBSUPPORT at any ! prompt.

Visit our Web page at www.interactiv.com

Call us at (416) 977-5550.

Using the BBS?

Don't forget to set your modem to 8 data bits, no parity and 1 stop bit. Use any baud rate between 1200 and 14,400.


Changes to Logic Analyzer

The time-based logic analyzer has been changed to display the number of clocks per division instead of the number of seconds per division.

Instead of storing all the time points it receives, the logic analyzer only stores the time points under one of two conditions:

when the external clock triggers in external clock mode

when the internal clock triggers, spaced at a certain internal clock frequency in internal clock mode.

The internal clock frequency can be set in the clock setup dialog box (this wasn't allowed before).

The pre-trigger, post-trigger and voltage threshold values, which previously could only be modified in the analysis options' instruments tab dialog box, can now be set in the clock setup dialog box.

The logic analyzer voltage threshold value will modify that characteristic (this was not the case previously).

When the "clocks per division" setting is modified, the display is updated to reflect the change. If the number of clocks per division exceeds 16 clks/div, the logic analyzer will not display all of the time points, since there are only 16 pixels per division. For example, if the setting is 32 clks/div, there are two time points for every pixel in a division. To deal with this case, the logic analyzer will display the value of the first time point at each pixel. The same method will be employed to display 64 clks/div and 128 clks/div. The actual time between two points on the display can be determined using the cursors.

Note:  The time displayed when a cursor is located between two clock triggers is not necessarily accurate. This time is calculated by linearly interpolating between the actual times recorded at the time point that occurred closest to when the clock (external or internal) had triggered.

The external clock input and qualifier function properly now. Previously if the external clock triggered and did not trigger again for a long period of time, all the time points between the first and second trigger would be displayed. However, none of those time points between the first and second clock trigger should appear now.

The time period between each time point generated by a simulation varies from circuit to circuit. If, for example, the simulation of a circuit generated time points at a frequency of 1kHz, but the internal clock frequency of the logic analyzer was set to 10 kHz, and the "clocks per division" parameter was set to 1 clock per division, the traces displayed may be misleading. An instance of where this could happen is if the word generator output terminals are hooked up directly to the input terminals of the logic analyzer and set to count up from zero at a frequency of 1 kHz while the logic analyzer is set to sample at 10kHz. Theoretically, the time interval for 1 division on the logic analyzer should be 0.1 ms in this case, but it will actually be greater, since the logic analyzer can only sample at a maximum rate of 1 kHz as limited by the simulation. It is recommended that the internal clock rate be lowered in these cases, to avoid confusion.


Revisions to Version 5 Documentation

Electronics Workbench User's Guide

Page 3-8	After activating the circuit in step 1 you should get voltage readings of 735.7 mV across the LED and the ammeter should read 22.53 mA, not 1.77 V across the LED and 20.53 mA on the ammeter.
Page 4-4	Step 4 in Setting the Analysis Options of the Oscilloscope states: Select "Use initial conditions". This should say: Select "User-defined".
Page 4-5	The equation in the paragraph Electronics Concepts Demonstrated states: TC = 10kW x 20 mF = 0.2 seconds. The equation should state:
Page 4-11	The figure shown indicates that the output of the Bode Plotter is connected to connector "C" of the circuit. This is an error. The output should be connected to connector "B". Furthermore, you should use an AC Source instead of a Function Generator to provide the input signal to the circuit.
Page 5-11	The last paragraph in "The Next Step" indicates Electronics Workbench User's Reference. This should, instead, reference the Electronics Workbench Technical Reference.
Page 6-9	The graphic shown under Fault Tab is, in fact, the Node tab. The text description in this section is accurate for the Fault tab, however.
Page B-1	Under Transferring Macintosh Circuits to a PC, step 1 states that "The circuit must have an extension of .ewb." This is true if the circuit was created in Electronics Workbench Version 5 for Macintosh. If you have a circuit created in Electronics Workbench Version 4 for Macintosh, the extension given to the circuit must be .ca4.

Electronics Workbench Technical Reference

Page 7-3	Under Monostable Multivibrator, the second-last paragraph states "The output of Y will give a pulse of duration 0.0693*R*C ...". The statement should read "The output of Q will give a pulse of duration 0.0693*R*C ...".
Page 9-7	Under the Schmitt Trigger, the first sentence states "This component is a type of multivibrator circuit that produces ...". The first sentence should state " This component is a type of comparator with hysteresis that produces ...". Furthermore, under characteristic operation, the outputs "1" and "0" should be switched. Therefore, the Schmitt trigger outputs "0" if the voltage is rising and  and  "1"  if the voltage is falling and
Page 12-3	The equation in the Characteristic Equations section under Transfer Function Block is incomplete. The following equation should be used:
Page 14-3	Under Signal Mode (AC or DC), the RMS Voltage equation should be: RMS voltage =
Page 14-12	The title of the Trigger Level is incorrect. The title should read: "Trigger Level (-3.00 - 3.00).